Nested VMX: Flush TLBs and Caches if paging mode changed

According to SDM, if paging mode is changed, then whole TLBs and caches will
be flushed. This is missed in nested handle logic. Also this fixed the issue
that 64 bits windows cannot boot up on top of L1 kvm.

Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
Acked-by: Keir Fraser <keir@xen.org>

diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c
index cd08b2a2049af7dad10c5e4a2897f2542ff9a5c0..4ba7669a340c2e91fa177c4abc3752bad8f0a31b 100644 (file)
--- a/xen/arch/x86/mm/paging.c
+++ b/xen/arch/x86/mm/paging.c
@@ -709,6 +709,7 @@ void paging_update_nestedmode(struct vcpu *v)
     else
         /* TODO: shadow-on-shadow */
         v->arch.paging.nestedmode = NULL;
+    hvm_asid_flush_vcpu(v);
 }
 
 void paging_write_p2m_entry(struct p2m_domain *p2m, unsigned long gfn,