}
}
-int force_mwait __cpuinitdata;
+int force_mwait;
static void disable_c1e(void *unused)
{
#include "cpu.h"
-static bool_t __cpuinitdata use_xsave = 1;
+static bool_t use_xsave = 1;
boolean_param("xsave", use_xsave);
bool_t __devinitdata opt_arat = 1;
*/
u64 host_pat = 0x050100070406;
-static unsigned int __cpuinitdata cleared_caps[NCAPINTS];
+static unsigned int cleared_caps[NCAPINTS];
void __init setup_clear_cpu_cap(unsigned int cap)
{
};
/* all the cache descriptor types we care about (no TLB or trace cache entries) */
-static struct _cache_table cache_table[] __cpuinitdata =
+static struct _cache_table cache_table[] =
{
{ 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
{ 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
/*
* Keep BIOS's CPU2node information, should not be used for memory allocaion
*/
-nodeid_t apicid_to_node[MAX_LOCAL_APIC] __cpuinitdata = {
+nodeid_t apicid_to_node[MAX_LOCAL_APIC] = {
[0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE
};
cpumask_t node_to_cpumask[MAX_NUMNODES] __read_mostly;
u32 device;
};
-static u64 __cpuinitdata fam10h_pci_mmconf_base;
+static u64 fam10h_pci_mmconf_base;
-static struct pci_hostbridge_probe pci_probes[] __cpuinitdata = {
+static struct pci_hostbridge_probe pci_probes[] = {
{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
};
#define mk_unsigned_long(x) x
#endif /* !__ASSEMBLY__ */
-#define __cpuinitdata
#define __cpuinit
#ifdef FLASK_ENABLE