x86: Pass through ERMS CPUID feature for HVM and PV guests

This patch exposes ERMS feature to HVM and PV guests.

The REP MOVSB/STOSB instruction can enhance fast strings attempts to
move as much of the data with larger size load/stores as possible.

Signed-off-by: Yang, Wei <wei.y.yang@intel.com>

diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h
index b1941f9956d7262652802fbc69995dd55795acf6..96a44ff59f98102f6abd8d911f01dfad1daaa704 100644 (file)
--- a/tools/libxc/xc_cpufeature.h
+++ b/tools/libxc/xc_cpufeature.h
@@ -126,5 +126,6 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
 #define X86_FEATURE_FSGSBASE     0 /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_SMEP         7 /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_ERMS         9 /* Enhanced REP MOVSB/STOSB */
 
 #endif /* __LIBXC_CPUFEATURE_H */

diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 287b1e77898975b1359357b5a8f3629f47726e59..d791691e693971a17adbff1873527b0879eec188 100644 (file)
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -355,7 +355,8 @@ static void xc_cpuid_hvm_policy(
 
     case 0x00000007: /* Intel-defined CPU features */
         if ( input[1] == 0 ) {
-            regs[1] &= bitmaskof(X86_FEATURE_SMEP);
+            regs[1] &= (bitmaskof(X86_FEATURE_SMEP) |
+                        bitmaskof(X86_FEATURE_ERMS));
         } else
             regs[1] = 0;
         regs[0] = regs[2] = regs[3] = 0;
@@ -478,7 +479,8 @@ static void xc_cpuid_pv_policy(
 
     case 7:
         if ( input[1] == 0 )
-            regs[1] &= bitmaskof(X86_FEATURE_FSGSBASE);
+            regs[1] &= (bitmaskof(X86_FEATURE_FSGSBASE) |
+                        bitmaskof(X86_FEATURE_ERMS));
         else
             regs[1] = 0;
         regs[0] = regs[2] = regs[3] = 0;

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 383fb5e72a25ca4f2f8ae828a6af56c14dfec90e..512dec3d8eb1da1ea1821bf0939e9b76d14fd21a 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -815,7 +815,8 @@ static void pv_cpuid(struct cpu_user_regs *regs)
         break;
     case 7:
         if ( regs->ecx == 0 )
-            b &= cpufeat_mask(X86_FEATURE_FSGSBASE);
+            b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
+                  cpufeat_mask(X86_FEATURE_ERMS));
         else
             b = 0;
         a = c = d = 0;

diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index f76a08f5be035fb5b94a118572cdf35ff1b6690b..3e6d4c5c801f706e5f57e72293573f8d461546a8 100644 (file)
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -145,6 +145,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
 #define X86_FEATURE_FSGSBASE   (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_SMEP       (7*32+ 7) /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_ERMS       (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
 
 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)