}
#if CONFIG_HVM
-static int vmce_save_vcpu_ctxt_one(struct vcpu *v, hvm_domain_context_t *h)
+static int vmce_save_vcpu_ctxt(struct vcpu *v, hvm_domain_context_t *h)
{
struct hvm_vmce_vcpu ctxt = {
.caps = v->arch.vmce.mcg_cap,
return hvm_save_entry(VMCE_VCPU, v->vcpu_id, h, &ctxt);
}
-static int vmce_save_vcpu_ctxt(struct domain *d, hvm_domain_context_t *h)
-{
- struct vcpu *v;
- int err = 0;
-
- for_each_vcpu ( d, v )
- {
- err = vmce_save_vcpu_ctxt_one(v, h);
- if ( err )
- break;
- }
-
- return err;
-}
-
static int vmce_load_vcpu_ctxt(struct domain *d, hvm_domain_context_t *h)
{
unsigned int vcpuid = hvm_load_instance(h);
}
HVM_REGISTER_SAVE_RESTORE(VMCE_VCPU, vmce_save_vcpu_ctxt,
- vmce_save_vcpu_ctxt_one,
vmce_load_vcpu_ctxt, 1, HVMSR_PER_VCPU);
#endif
spin_unlock(&pit->lock);
}
-static int pit_save(struct domain *d, hvm_domain_context_t *h)
+static int pit_save(struct vcpu *v, hvm_domain_context_t *h)
{
+ struct domain *d = v->domain;
PITState *pit = domain_vpit(d);
int rc;
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(PIT, pit_save, NULL, pit_load, 1, HVMSR_PER_DOM);
+HVM_REGISTER_SAVE_RESTORE(PIT, pit_save, pit_load, 1, HVMSR_PER_DOM);
#endif
void pit_reset(struct domain *d)
};
-static int hpet_save(struct domain *d, hvm_domain_context_t *h)
+static int hpet_save(struct vcpu *v, hvm_domain_context_t *h)
{
+ const struct domain *d = v->domain;
HPETState *hp = domain_vhpet(d);
- struct vcpu *v = pt_global_vcpu_target(d);
int rc;
uint64_t guest_time;
if ( !has_vhpet(d) )
return 0;
+ v = pt_global_vcpu_target(d);
write_lock(&hp->lock);
guest_time = (v->arch.hvm.guest_time ?: hvm_get_guest_time(v)) /
STIME_PER_HPET_TICK;
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(HPET, hpet_save, NULL, hpet_load, 1, HVMSR_PER_DOM);
+HVM_REGISTER_SAVE_RESTORE(HPET, hpet_save, hpet_load, 1, HVMSR_PER_DOM);
static void hpet_set(HPETState *h)
{
destroy_vpci_mmcfg(d);
}
-static int hvm_save_tsc_adjust_one(struct vcpu *v, hvm_domain_context_t *h)
+static int hvm_save_tsc_adjust(struct vcpu *v, hvm_domain_context_t *h)
{
struct hvm_tsc_adjust ctxt = {
.tsc_adjust = v->arch.hvm.msr_tsc_adjust,
return hvm_save_entry(TSC_ADJUST, v->vcpu_id, h, &ctxt);
}
-static int hvm_save_tsc_adjust(struct domain *d, hvm_domain_context_t *h)
-{
- struct vcpu *v;
- int err = 0;
-
- for_each_vcpu ( d, v )
- {
- err = hvm_save_tsc_adjust_one(v, h);
- if ( err )
- break;
- }
-
- return err;
-}
-
static int hvm_load_tsc_adjust(struct domain *d, hvm_domain_context_t *h)
{
unsigned int vcpuid = hvm_load_instance(h);
}
HVM_REGISTER_SAVE_RESTORE(TSC_ADJUST, hvm_save_tsc_adjust,
- hvm_save_tsc_adjust_one,
hvm_load_tsc_adjust, 1, HVMSR_PER_VCPU);
-static int hvm_save_cpu_ctxt_one(struct vcpu *v, hvm_domain_context_t *h)
+static int hvm_save_cpu_ctxt(struct vcpu *v, hvm_domain_context_t *h)
{
struct segment_register seg;
struct hvm_hw_cpu ctxt = {
return hvm_save_entry(CPU, v->vcpu_id, h, &ctxt);
}
-static int hvm_save_cpu_ctxt(struct domain *d, hvm_domain_context_t *h)
-{
- struct vcpu *v;
- int err = 0;
-
- for_each_vcpu ( d, v )
- {
- err = hvm_save_cpu_ctxt_one(v, h);
- if ( err )
- break;
- }
-
- return err;
-}
-
/* Return a string indicating the error, or NULL for valid. */
const char *hvm_efer_valid(const struct vcpu *v, uint64_t value,
signed int cr0_pg)
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(CPU, hvm_save_cpu_ctxt, hvm_save_cpu_ctxt_one,
- hvm_load_cpu_ctxt, 1, HVMSR_PER_VCPU);
+HVM_REGISTER_SAVE_RESTORE(CPU, hvm_save_cpu_ctxt, hvm_load_cpu_ctxt, 1,
+ HVMSR_PER_VCPU);
#define HVM_CPU_XSAVE_SIZE(xcr0) (offsetof(struct hvm_hw_cpu_xsave, \
save_area) + \
xstate_ctxt_size(xcr0))
-static int hvm_save_cpu_xsave_states_one(struct vcpu *v, hvm_domain_context_t *h)
+static int hvm_save_cpu_xsave_states(struct vcpu *v, hvm_domain_context_t *h)
{
struct hvm_hw_cpu_xsave *ctxt;
unsigned int size = HVM_CPU_XSAVE_SIZE(v->arch.xcr0_accum);
return 0;
}
-static int hvm_save_cpu_xsave_states(struct domain *d, hvm_domain_context_t *h)
-{
- struct vcpu *v;
- int err = 0;
-
- for_each_vcpu ( d, v )
- {
- err = hvm_save_cpu_xsave_states_one(v, h);
- if ( err )
- break;
- }
-
- return err;
-}
-
/*
* Structure layout conformity checks, documenting correctness of the cast in
* the invocation of validate_xstate() below.
};
static unsigned int __read_mostly msr_count_max = ARRAY_SIZE(msrs_to_send);
-static int hvm_save_cpu_msrs_one(struct vcpu *v, hvm_domain_context_t *h)
+static int hvm_save_cpu_msrs(struct vcpu *v, hvm_domain_context_t *h)
{
struct hvm_save_descriptor *desc = _p(&h->data[h->cur]);
struct hvm_msr *ctxt;
return 0;
}
-static int hvm_save_cpu_msrs(struct domain *d, hvm_domain_context_t *h)
-{
- struct vcpu *v;
- int err = 0;
-
- for_each_vcpu ( d, v )
- {
- err = hvm_save_cpu_msrs_one(v, h);
- if ( err )
- break;
- }
-
- return err;
-}
-
static int hvm_load_cpu_msrs(struct domain *d, hvm_domain_context_t *h)
{
unsigned int i, vcpuid = hvm_load_instance(h);
hvm_register_savevm(CPU_XSAVE_CODE,
"CPU_XSAVE",
hvm_save_cpu_xsave_states,
- hvm_save_cpu_xsave_states_one,
hvm_load_cpu_xsave_states,
HVM_CPU_XSAVE_SIZE(xfeature_mask) +
sizeof(struct hvm_save_descriptor),
hvm_register_savevm(CPU_MSR_CODE,
"CPU_MSR",
hvm_save_cpu_msrs,
- hvm_save_cpu_msrs_one,
hvm_load_cpu_msrs,
HVM_CPU_MSR_SIZE(msr_count_max) +
sizeof(struct hvm_save_descriptor),
}
__initcall(dump_irq_info_key_init);
-static int irq_save_pci(struct domain *d, hvm_domain_context_t *h)
+static int irq_save_pci(struct vcpu *v, hvm_domain_context_t *h)
{
+ struct domain *d = v->domain;
struct hvm_irq *hvm_irq = hvm_domain_irq(d);
unsigned int asserted, pdev, pintx;
int rc;
return rc;
}
-static int irq_save_isa(struct domain *d, hvm_domain_context_t *h)
+static int irq_save_isa(struct vcpu *v, hvm_domain_context_t *h)
{
+ const struct domain *d = v->domain;
struct hvm_irq *hvm_irq = hvm_domain_irq(d);
/* Save ISA IRQ lines */
return ( hvm_save_entry(ISA_IRQ, 0, h, &hvm_irq->isa_irq) );
}
-static int irq_save_link(struct domain *d, hvm_domain_context_t *h)
+static int irq_save_link(struct vcpu *v, hvm_domain_context_t *h)
{
+ const struct domain *d = v->domain;
struct hvm_irq *hvm_irq = hvm_domain_irq(d);
/* Save PCI-ISA link state */
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(PCI_IRQ, irq_save_pci, NULL, irq_load_pci,
+HVM_REGISTER_SAVE_RESTORE(PCI_IRQ, irq_save_pci, irq_load_pci,
1, HVMSR_PER_DOM);
-HVM_REGISTER_SAVE_RESTORE(ISA_IRQ, irq_save_isa, NULL, irq_load_isa,
+HVM_REGISTER_SAVE_RESTORE(ISA_IRQ, irq_save_isa, irq_load_isa,
1, HVMSR_PER_DOM);
-HVM_REGISTER_SAVE_RESTORE(PCI_LINK, irq_save_link, NULL, irq_load_link,
+HVM_REGISTER_SAVE_RESTORE(PCI_LINK, irq_save_link, irq_load_link,
1, HVMSR_PER_DOM);
return 0;
}
-static int hvm_save_mtrr_msr_one(struct vcpu *v, hvm_domain_context_t *h)
+static int hvm_save_mtrr_msr(struct vcpu *v, hvm_domain_context_t *h)
{
const struct mtrr_state *mtrr_state = &v->arch.hvm.mtrr;
struct hvm_hw_mtrr hw_mtrr = {
return hvm_save_entry(MTRR, v->vcpu_id, h, &hw_mtrr);
}
-static int hvm_save_mtrr_msr(struct domain *d, hvm_domain_context_t *h)
-{
- struct vcpu *v;
- int err = 0;
-
- /* save mtrr&pat */
- for_each_vcpu(d, v)
- {
- err = hvm_save_mtrr_msr_one(v, h);
- if ( err )
- break;
- }
-
- return err;
-}
-
static int hvm_load_mtrr_msr(struct domain *d, hvm_domain_context_t *h)
{
unsigned int vcpuid, i;
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(MTRR, hvm_save_mtrr_msr, hvm_save_mtrr_msr_one,
- hvm_load_mtrr_msr, 1, HVMSR_PER_VCPU);
+HVM_REGISTER_SAVE_RESTORE(MTRR, hvm_save_mtrr_msr, hvm_load_mtrr_msr, 1,
+ HVMSR_PER_VCPU);
void memory_type_changed(struct domain *d)
{
return X86EMUL_OKAY;
}
-static int acpi_save(struct domain *d, hvm_domain_context_t *h)
+static int acpi_save(struct vcpu *v, hvm_domain_context_t *h)
{
+ struct domain *d = v->domain;
struct hvm_hw_acpi *acpi = &d->arch.hvm.acpi;
PMTState *s = &d->arch.hvm.pl_time->vpmt;
uint32_t x, msb = acpi->tmr_val & TMR_VAL_MSB;
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(PMTIMER, acpi_save, NULL, acpi_load,
+HVM_REGISTER_SAVE_RESTORE(PMTIMER, acpi_save, acpi_load,
1, HVMSR_PER_DOM);
int pmtimer_change_ioport(struct domain *d, unsigned int version)
}
/* Save RTC hardware state */
-static int rtc_save(struct domain *d, hvm_domain_context_t *h)
+static int rtc_save(struct vcpu *v, hvm_domain_context_t *h)
{
+ const struct domain *d = v->domain;
RTCState *s = domain_vrtc(d);
int rc;
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(RTC, rtc_save, NULL, rtc_load, 1, HVMSR_PER_DOM);
+HVM_REGISTER_SAVE_RESTORE(RTC, rtc_save, rtc_load, 1, HVMSR_PER_DOM);
void rtc_reset(struct domain *d)
{
/* List of handlers for various HVM save and restore types */
static struct {
hvm_save_handler save;
- hvm_save_vcpu_handler save_one;
hvm_load_handler load;
const char *name;
size_t size;
void __init hvm_register_savevm(uint16_t typecode,
const char *name,
hvm_save_handler save_state,
- hvm_save_vcpu_handler save_one,
hvm_load_handler load_state,
size_t size, int kind)
{
ASSERT(hvm_sr_handlers[typecode].save == NULL);
ASSERT(hvm_sr_handlers[typecode].load == NULL);
hvm_sr_handlers[typecode].save = save_state;
- hvm_sr_handlers[typecode].save_one = save_one;
hvm_sr_handlers[typecode].load = load_state;
hvm_sr_handlers[typecode].name = name;
hvm_sr_handlers[typecode].size = size;
int rv;
hvm_domain_context_t ctxt = { };
const struct hvm_save_descriptor *desc;
+ struct vcpu *v;
if ( d->is_dying ||
typecode > HVM_SAVE_CODE_MAX ||
!hvm_sr_handlers[typecode].save )
return -EINVAL;
+ if ( hvm_sr_handlers[typecode].kind != HVMSR_PER_VCPU )
+ v = d->vcpu[0];
+ else if ( instance >= d->max_vcpus || !d->vcpu[instance] )
+ return -ENOENT;
+ else
+ v = d->vcpu[instance];
ctxt.size = hvm_sr_handlers[typecode].size;
- if ( hvm_sr_handlers[typecode].kind == HVMSR_PER_VCPU )
- ctxt.size *= d->max_vcpus;
ctxt.data = xmalloc_bytes(ctxt.size);
if ( !ctxt.data )
return -ENOMEM;
- if ( (rv = hvm_sr_handlers[typecode].save(d, &ctxt)) != 0 )
+ if ( (rv = hvm_sr_handlers[typecode].save(v, &ctxt)) != 0 )
printk(XENLOG_G_ERR "HVM%d save: failed to save type %"PRIu16" (%d)\n",
d->domain_id, typecode, rv);
else if ( rv = -ENOENT, ctxt.cur >= sizeof(*desc) )
/* Save all available kinds of state */
for ( i = 0; i <= HVM_SAVE_CODE_MAX; i++ )
{
- hvm_save_vcpu_handler save_one_handler = hvm_sr_handlers[i].save_one;
hvm_save_handler handler = hvm_sr_handlers[i].save;
- if ( save_one_handler )
+ if ( !handler )
+ continue;
+
+ if ( hvm_sr_handlers[i].kind == HVMSR_PER_VCPU )
{
struct vcpu *v;
{
printk(XENLOG_G_INFO "HVM %pv save: %s\n",
v, hvm_sr_handlers[i].name);
- if ( save_one_handler(v, h) != 0 )
+ if ( handler(v, h) != 0 )
{
printk(XENLOG_G_ERR
"HVM %pv save: failed to save type %"PRIu16"\n",
}
}
}
- else if ( handler )
+ else
{
- printk(XENLOG_G_INFO "HVM%d save: %s\n",
+ printk(XENLOG_G_INFO "HVM d%d save: %s\n",
d->domain_id, hvm_sr_handlers[i].name);
- if ( handler(d, h) != 0 )
+ if ( handler(d->vcpu[0], h) != 0 )
{
printk(XENLOG_G_ERR
- "HVM%d save: failed to save type %"PRIu16"\n",
+ "HVM d%d save: failed to save type %"PRIu16"\n",
d->domain_id, i);
return -ENODATA;
}
return vioapic->redirtbl[pin].fields.trig_mode;
}
-static int ioapic_save(struct domain *d, hvm_domain_context_t *h)
+static int ioapic_save(struct vcpu *v, hvm_domain_context_t *h)
{
+ const struct domain *d = v->domain;
struct hvm_vioapic *s;
if ( !has_vioapic(d) )
return hvm_load_entry(IOAPIC, h, &s->domU);
}
-HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, NULL, ioapic_load, 1, HVMSR_PER_DOM);
+HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, ioapic_load, 1, HVMSR_PER_DOM);
void vioapic_reset(struct domain *d)
{
return HVM_HCALL_completed;
}
-static int viridian_save_domain_ctxt(struct domain *d, hvm_domain_context_t *h)
+static int viridian_save_domain_ctxt(struct vcpu *v, hvm_domain_context_t *h)
{
+ const struct domain *d = v->domain;
struct hvm_viridian_domain_context ctxt = {
.time_ref_count = d->arch.hvm.viridian.time_ref_count.val,
.hypercall_gpa = d->arch.hvm.viridian.hypercall_gpa.raw,
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(VIRIDIAN_DOMAIN, viridian_save_domain_ctxt, NULL,
+HVM_REGISTER_SAVE_RESTORE(VIRIDIAN_DOMAIN, viridian_save_domain_ctxt,
viridian_load_domain_ctxt, 1, HVMSR_PER_DOM);
-static int viridian_save_vcpu_ctxt_one(struct vcpu *v, hvm_domain_context_t *h)
+static int viridian_save_vcpu_ctxt(struct vcpu *v, hvm_domain_context_t *h)
{
struct hvm_viridian_vcpu_context ctxt = {
.vp_assist_msr = v->arch.hvm.viridian.vp_assist.msr.raw,
return hvm_save_entry(VIRIDIAN_VCPU, v->vcpu_id, h, &ctxt);
}
-static int viridian_save_vcpu_ctxt(struct domain *d, hvm_domain_context_t *h)
-{
- struct vcpu *v;
- int err = 0;
-
- for_each_vcpu ( d, v )
- {
- err = viridian_save_vcpu_ctxt_one(v, h);
- if ( err )
- break;
- }
-
- return err;
-}
-
static int viridian_load_vcpu_ctxt(struct domain *d, hvm_domain_context_t *h)
{
unsigned int vcpuid = hvm_load_instance(h);
}
HVM_REGISTER_SAVE_RESTORE(VIRIDIAN_VCPU, viridian_save_vcpu_ctxt,
- viridian_save_vcpu_ctxt_one,
viridian_load_vcpu_ctxt, 1, HVMSR_PER_VCPU);
static int __init parse_viridian_version(const char *arg)
s->timer_last_update = s->pt.last_plt_gtime;
}
-static int lapic_save_hidden_one(struct vcpu *v, hvm_domain_context_t *h)
+static int lapic_save_hidden(struct vcpu *v, hvm_domain_context_t *h)
{
if ( !has_vlapic(v->domain) )
return 0;
return hvm_save_entry(LAPIC, v->vcpu_id, h, &vcpu_vlapic(v)->hw);
}
-static int lapic_save_hidden(struct domain *d, hvm_domain_context_t *h)
-{
- struct vcpu *v;
- int err = 0;
-
- for_each_vcpu ( d, v )
- {
- err = lapic_save_hidden_one(v, h);
- if ( err )
- break;
- }
-
- return err;
-}
-
-static int lapic_save_regs_one(struct vcpu *v, hvm_domain_context_t *h)
+static int lapic_save_regs(struct vcpu *v, hvm_domain_context_t *h)
{
if ( !has_vlapic(v->domain) )
return 0;
return hvm_save_entry(LAPIC_REGS, v->vcpu_id, h, vcpu_vlapic(v)->regs);
}
-static int lapic_save_regs(struct domain *d, hvm_domain_context_t *h)
-{
- struct vcpu *v;
- int err = 0;
-
- for_each_vcpu ( d, v )
- {
- err = lapic_save_regs_one(v, h);
- if ( err )
- break;
- }
-
- return err;
-}
-
/*
* Following lapic_load_hidden()/lapic_load_regs() we may need to
* correct ID and LDR when they come from an old, broken hypervisor.
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(LAPIC, lapic_save_hidden, lapic_save_hidden_one,
+HVM_REGISTER_SAVE_RESTORE(LAPIC, lapic_save_hidden,
lapic_load_hidden, 1, HVMSR_PER_VCPU);
-HVM_REGISTER_SAVE_RESTORE(LAPIC_REGS, lapic_save_regs, lapic_save_regs_one,
+HVM_REGISTER_SAVE_RESTORE(LAPIC_REGS, lapic_save_regs,
lapic_load_regs, 1, HVMSR_PER_VCPU);
int vlapic_init(struct vcpu *v)
return X86EMUL_OKAY;
}
-static int vpic_save(struct domain *d, hvm_domain_context_t *h)
+static int vpic_save(struct vcpu *v, hvm_domain_context_t *h)
{
+ struct domain *d = v->domain;
struct hvm_hw_vpic *s;
int i;
return 0;
}
-HVM_REGISTER_SAVE_RESTORE(PIC, vpic_save, NULL, vpic_load, 2, HVMSR_PER_DOM);
+HVM_REGISTER_SAVE_RESTORE(PIC, vpic_save, vpic_load, 2, HVMSR_PER_DOM);
void vpic_reset(struct domain *d)
{
* The save handler may save multiple instances of a type into the buffer;
* the load handler will be called once for each instance found when
* restoring. Both return non-zero on error. */
-typedef int (*hvm_save_handler) (struct domain *d,
+typedef int (*hvm_save_handler) (struct vcpu *v,
hvm_domain_context_t *h);
-typedef int (*hvm_save_vcpu_handler)(struct vcpu *v,
- hvm_domain_context_t *h);
typedef int (*hvm_load_handler) (struct domain *d,
hvm_domain_context_t *h);
void hvm_register_savevm(uint16_t typecode,
const char *name,
hvm_save_handler save_state,
- hvm_save_vcpu_handler save_one,
hvm_load_handler load_state,
size_t size, int kind);
/* Syntactic sugar around that function: specify the max number of
* saves, and this calculates the size of buffer needed */
-#define HVM_REGISTER_SAVE_RESTORE(_x, _save, _save_one, _load, _num, _k) \
+#define HVM_REGISTER_SAVE_RESTORE(_x, _save, _load, _num, _k) \
static int __init __hvm_register_##_x##_save_and_restore(void) \
{ \
hvm_register_savevm(HVM_SAVE_CODE(_x), \
#_x, \
&_save, \
- _save_one, \
&_load, \
(_num) * (HVM_SAVE_LENGTH(_x) \
+ sizeof (struct hvm_save_descriptor)), \