Manual merge of version 2.0-2+rpi1 and 2.1-1 to produce 2.1-1+rpi1
authorPeter Michael Green <plugwash@raspbian.org>
Thu, 1 Mar 2018 16:36:29 +0000 (16:36 +0000)
committerPeter Michael Green <plugwash@raspbian.org>
Thu, 1 Mar 2018 16:36:29 +0000 (16:36 +0000)
1  2 
debian/changelog
debian/patches/series
debian/rules
vacall/vacall-armhf-macro.S

index f81fff5fd5b633888810ec318e0a4aea12acff5d,908861e3d249ae36feba139127e0f0d7cd0668c3..bbdfdadbd28311438e0c75b36f855507ea5cadc2
@@@ -1,10 -1,15 +1,24 @@@
- ffcall (2.0-2+rpi1) buster-staging; urgency=medium
++ffcall (2.1-1+rpi1) buster-staging; urgency=medium
 +
++  [changes brought forward from 2.0-2+rpi1 by Peter Michael Green <plugwash@raspbian.org> at Thu, 07 Dec 2017 01:23:49 +0000]
 +  * Replace movw/movt with ldr psuedo instruction.
 +  * Mark binaries as armv6 not armv7
 +  * Disable testsuite, it fails on some of our buildboxes.
 +
-  -- Peter Michael Green <plugwash@raspbian.org>  Thu, 07 Dec 2017 01:23:49 +0000
++ -- Raspbian forward porter <root@raspbian.org>  Thu, 01 Mar 2018 16:23:45 +0000
++
+ ffcall (2.1-1) unstable; urgency=medium
+   * New upstream release.
+   * Update Vcs-* fields for move to salsa.
+   * Drop fix-powerpcspe.patch, outdated, no longer works.
+   * Drop trampoline-mips64el.patch, applied upstream.
+   * No longer disable PIE on armhf, not needed anymore.
+   * Bump to debhelper compat level 11.
+   * Bump Standards-Version to 4.1.3.
+   * d/copyright: reflect upstream changes.
+  -- Sébastien Villemot <sebastien@debian.org>  Sat, 17 Feb 2018 21:30:10 +0100
  
  ffcall (2.0-2) unstable; urgency=medium
  
index 701c76efe1fc4c8f7a15dbead4db6da2ba3117bc,1038e0736719bc8abc3429326f579484b1b86fcf..ad6cb95e392a6e689bd5a93531edbadf9f83c593
@@@ -1,4 -1,1 +1,2 @@@
- fix-powerpcspe.patch
  mips-fpxx.patch
- trampoline-mips64el.patch
 +raspbian.patch
diff --cc debian/rules
Simple merge
index 031ff1c7ef39206607aaccb41d1530be3c77f0ff,c6628bfb6e23735c7ce233b46fc253e5ef6b81e5..4b9c6176558414c61f883617f82a8e9890742f29
  #include "asm-arm.h"
 -      .arch armv7-a
+ #ifdef __PIC__
 -      .arch armv7-a
++      .arch armv6
+       .eabi_attribute 28, 1
+       .eabi_attribute 20, 1
+       .eabi_attribute 21, 1
+       .eabi_attribute 23, 3
+       .eabi_attribute 24, 1
+       .eabi_attribute 25, 1
+       .eabi_attribute 26, 1
+       .eabi_attribute 30, 2
+       .eabi_attribute 34, 1
+       .eabi_attribute 18, 4
+       .text
+       .align  2
+       .global C(vacall_receiver)
+       .syntax unified
+       .arm
+       .fpu vfpv3-d16
+       .type   vacall_receiver, %function
+ FUNBEGIN(vacall_receiver)
+       // args = 20, pretend = 16, frame = 176
+       // frame_needed = 1, uses_anonymous_args = 0
+       sub     sp, sp, $16
+       mov     ip, $0
+       push    {r4, r5, r6, fp, lr}
+       add     fp, sp, $16
+       add     lr, fp, $4
+       sub     sp, sp, $180
+       ldr     r4, L(31)
+       add     r6, fp, $20
+       vstr.32 s0, [fp, $-152]
+       stm     lr, {r0, r1, r2, r3}
+ L(PIC0):
+       add     r4, pc, r4
+       vstr.32 s1, [fp, $-148]
+       sub     r0, fp, $196
+       str     lr, [fp, $-164]
+       str     ip, [fp, $-196]
+       vstr.32 s2, [fp, $-144]
+       str     ip, [fp, $-160]
+       str     r6, [fp, $-180]
+       vstr.32 s3, [fp, $-140]
+       ldr     r5, L(31)+4
+       vstr.32 s4, [fp, $-136]
+       vstr.32 s5, [fp, $-132]
+       vstr.32 s6, [fp, $-128]
+       vstr.32 s7, [fp, $-124]
+       vstr.32 s8, [fp, $-120]
+       vstr.32 s9, [fp, $-116]
+       vstr.32 s10, [fp, $-112]
+       vstr.32 s11, [fp, $-108]
+       vstr.32 s12, [fp, $-104]
+       vstr.32 s13, [fp, $-100]
+       vstr.32 s14, [fp, $-96]
+       vstr.32 s15, [fp, $-92]
+       vstr.64 d0, [fp, $-84]
+       vstr.64 d1, [fp, $-76]
+       vstr.64 d2, [fp, $-68]
+       vstr.64 d3, [fp, $-60]
+       vstr.64 d4, [fp, $-52]
+       vstr.64 d5, [fp, $-44]
+       vstr.64 d6, [fp, $-36]
+       str     ip, [fp, $-156]
+       str     ip, [fp, $-176]
+       vstr.64 d7, [fp, $-28]
+       strb    ip, [fp, $-172]
+       ldr     r3, [r4, r5]
+       ldr     r3, [r3]
+       blx     r3
+       ldrb    r3, [fp, $-172] // zero_extendqisi2
+       cmp     r3, $0
+       beq     L(1)
+       cmp     r3, $1
+       beq     L(25)
+       cmp     r3, $2
+       ldrsbeq r0, [fp, $-188]
+       beq     L(1)
+       cmp     r3, $3
+       beq     L(25)
+       cmp     r3, $4
+       ldrsheq r0, [fp, $-188]
+       beq     L(1)
+       cmp     r3, $5
+       ldrheq  r0, [fp, $-188]
+       beq     L(1)
+       cmp     r3, $6
+       beq     L(27)
+       cmp     r3, $7
+       beq     L(27)
+       cmp     r3, $8
+       beq     L(27)
+       cmp     r3, $9
+       beq     L(27)
+       sub     r2, r3, $10
+       cmp     r2, $1
+       bls     L(29)
+       cmp     r3, $12
+       vldreq.32       s0, [fp, $-188]
+       beq     L(1)
+       cmp     r3, $13
+       vldreq.64       d0, [fp, $-188]
+       beq     L(1)
+       cmp     r3, $14
+       beq     L(27)
+       cmp     r3, $15
+       bne     L(1)
+       ldr     r3, [fp, $-196]
+       tst     r3, $1024
+       beq     L(1)
+       ldr     r3, [fp, $-168]
+       cmp     r3, $1
+       beq     L(30)
+       cmp     r3, $2
+       ldr     r3, [fp, $-176]
+       ldrheq  r0, [r3]
+       ldrne   r0, [r3]
+ L(1):
+       sub     sp, fp, $16
+       // sp needed
+       pop     {r4, r5, r6, fp, lr}
+       add     sp, sp, $16
+       bx      lr
+ L(25):
+       ldrb    r0, [fp, $-188] // zero_extendqisi2
+       sub     sp, fp, $16
+       // sp needed
+       pop     {r4, r5, r6, fp, lr}
+       add     sp, sp, $16
+       bx      lr
+ L(27):
+       ldr     r0, [fp, $-188]
+       sub     sp, fp, $16
+       // sp needed
+       pop     {r4, r5, r6, fp, lr}
+       add     sp, sp, $16
+       bx      lr
+ L(29):
+       ldr     r0, [fp, $-188]
+       ldr     r1, [fp, $-184]
+       b       L(1)
+ L(30):
+       ldr     r3, [fp, $-176]
+       ldrb    r0, [r3]        // zero_extendqisi2
+       b       L(1)
+ L(32):
+       .align  2
+ L(31):
+       .word   _GLOBAL_OFFSET_TABLE_-(L(PIC0)+8)
+       .word   C(vacall_function)(GOT)
+       FUNEND(vacall_receiver)
+ #else
 +      .arch armv6
        .eabi_attribute 28, 1
        .eabi_attribute 20, 1
        .eabi_attribute 21, 1