memset(regs, 0, sizeof(*regs));
- regs->pc = (uint32_t)kinfo.entry;
-
- regs->cpsr = PSR_GUEST_INIT;
+ regs->pc = (register_t)kinfo.entry;
#ifdef CONFIG_ARM_64
d->arch.type = kinfo.type;
if ( is_pv32_domain(d) )
{
+ regs->cpsr = PSR_GUEST_INIT|PSR_MODE_SVC;
+
+ /* Pretend to be a Cortex A15 */
+ d->arch.vpidr = 0x410fc0f0;
+
/* FROM LINUX head.S
*
* Kernel startup entry point.
#ifdef CONFIG_ARM_64
else
{
+ regs->cpsr = PSR_GUEST_INIT|PSR_MODE_EL1h;
/* From linux/Documentation/arm64/booting.txt */
regs->x0 = kinfo.dtb_paddr;
regs->x1 = 0; /* Reserved for future use */
#define SCTLR_BASE 0x00c50078
#define HSCTLR_BASE 0x30c51878
+#define PSR_GUEST_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK)
+
/* HCR Hyp Configuration Register */
#define HCR_TGE (1<<27)
#define HCR_TVM (1<<26)
#define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */
#define PSR_JAZELLE (1<<24) /* Jazelle Mode */
-#define PSR_GUEST_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC)
-
#endif /* __XEN_PUBLIC_ARCH_ARM_H__ */
/*