vcpu_unblock(current);
}
+unsigned int domain_max_vcpus(const struct domain *d)
+{
+ /*
+ * Since evtchn_init would call domain_max_vcpus for poll_mask
+ * allocation when the vgic_ops haven't been initialised yet,
+ * we return MAX_VIRT_CPUS if d->arch.vgic.handler is null.
+ */
+ if ( !d->arch.vgic.handler )
+ return MAX_VIRT_CPUS;
+ else
+ return min_t(unsigned int, MAX_VIRT_CPUS,
+ d->arch.vgic.handler->max_vcpus);
+}
+
/*
* Local variables:
* mode: C
.domain_init = vgic_v2_domain_init,
.get_irq_priority = vgic_v2_get_irq_priority,
.get_target_vcpu = vgic_v2_get_target_vcpu,
+ .max_vcpus = 8,
};
int vgic_v2_init(struct domain *d)
.get_irq_priority = vgic_v3_get_irq_priority,
.get_target_vcpu = vgic_v3_get_target_vcpu,
.emulate_sysreg = vgic_v3_emulate_sysreg,
+ /*
+ * We use both AFF1 and AFF0 in (v)MPIDR. Thus, the max number of CPU
+ * that can be supported is up to 4096(==256*16) in theory.
+ */
+ .max_vcpus = 4096,
};
int vgic_v3_init(struct domain *d)
void vcpu_show_execution_state(struct vcpu *);
void vcpu_show_registers(const struct vcpu *);
-static inline unsigned int domain_max_vcpus(const struct domain *d)
-{
- return MAX_VIRT_CPUS;
-}
+unsigned int domain_max_vcpus(const struct domain *);
/*
* Due to the restriction of GICv3, the number of vCPUs in AFF0 is
struct vcpu *(*get_target_vcpu)(struct vcpu *v, unsigned int irq);
/* vGIC sysreg emulation */
int (*emulate_sysreg)(struct cpu_user_regs *regs, union hsr hsr);
+ /* Maximum number of vCPU supported */
+ const unsigned int max_vcpus;
};
/* Number of ranks of interrupt registers for a domain */