arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO

Origin: https://git.kernel.org/linus/3736aa7ecc4cd9b4abce30052bad00aba4f0362f

This patch enables the PCIe2 on the CM4IO board when paired with
a SOQuartz CM4 System-on-Module board. combphy2 also needs to be
enabled in this case to make the PHY work for this.

Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20221112160404.70868-5-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Gbp-Pq: Topic features/arm64/quartz64
Gbp-Pq: Name arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
index 6ba562b922e6cd8ff11cdf10446bd8307f98283a..cddf6cd2fecb1bf34458a98adc93b59560f98fde 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
@@ -40,6 +40,12 @@
        };
 };
 
+/* phy for pcie */
+&combphy2 {
+       phy-supply = <&vcc3v3_sys>;
+       status = "okay";
+};
+
 &gmac1 {
        status = "okay";
 };
@@ -115,6 +121,11 @@
        status = "okay";
 };
 
+&pcie2x1 {
+       vpcie3v3-supply = <&vcc_3v3>;
+       status = "okay";
+};
+
 &rgmii_phy1 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
index bcdc124328b3995cc7b59b30f8adf01234bc4ffb..31aa2b8efe39314087190027c495cb2b4a26c163 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
@@ -490,6 +490,12 @@
        };
 };
 
+&pcie2x1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_reset_h>;
+       reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+};
+
 &pinctrl {
        bt {
                bt_enable_h: bt-enable-h {
@@ -515,6 +521,15 @@
                };
        };
 
+       pcie {
+               pcie_clkreq_h: pcie-clkreq-h {
+                       rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+               pcie_reset_h: pcie-reset-h {
+                       rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
        pmic {
                pmic_int_l: pmic-int-l {
                        rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;