x86: MISALIGNSSE feature depends on SSE

Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Release-acked-by: Wei Liu <wei.liu2@citrix.com>

diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 33e68ebf648543f78578a4fc96111cf0913fcd0a..005cad9b43029ec3a5345c2738bdd5031dd18195 100755 (executable)
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -196,8 +196,9 @@ def crunch_numbers(state):
 
         # SSE is taken to mean support for the %XMM registers as well as the
         # instructions.  Several futher instruction sets are built on core
-        # %XMM support, without specific inter-dependencies.
-        SSE: [SSE2, SSE3, SSSE3, SSE4A,
+        # %XMM support, without specific inter-dependencies.  Additionally
+        # AMD has a special mis-alignment sub-mode.
+        SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE,
               AESNI, SHA],
 
         # SSE2 was re-specified as core instructions for 64bit.