break;
case MSR_INTEL_PLATFORM_INFO:
- *val = (uint64_t)dp->plaform_info.cpuid_faulting <<
- _MSR_PLATFORM_INFO_CPUID_FAULTING;
+ *val = dp->plaform_info.raw;
break;
case MSR_ARCH_CAPABILITIES:
goto gp_fault;
case MSR_INTEL_MISC_FEATURES_ENABLES:
- *val = (uint64_t)vp->misc_features_enables.cpuid_faulting <<
- _MSR_MISC_FEATURES_CPUID_FAULTING;
+ *val = vp->misc_features_enables.raw;
break;
default:
if ( val & rsvd )
goto gp_fault;
- vp->misc_features_enables.cpuid_faulting =
- val & MSR_MISC_FEATURES_CPUID_FAULTING;
+ vp->misc_features_enables.raw = val;
if ( v == curr && is_hvm_domain(d) && cpu_has_cpuid_faulting &&
(old_cpuid_faulting ^ vp->misc_features_enables.cpuid_faulting) )
* guests so can be offered unconditionally, while support for PV guests
* is dependent on real hardware support.
*/
- struct {
- bool cpuid_faulting;
+ union {
+ uint32_t raw;
+ struct {
+ uint32_t :31;
+ bool cpuid_faulting:1;
+ };
} plaform_info;
};
* unconditionally. The CPUID Faulting bit is the only writeable bit, and
* only if enumerated by MSR_PLATFORM_INFO.
*/
- struct {
- bool cpuid_faulting;
+ union {
+ uint32_t raw;
+ struct {
+ bool cpuid_faulting:1;
+ };
} misc_features_enables;
};