x86/pat: Simplify host PAT handling
authorAndrew Cooper <andrew.cooper3@citrix.com>
Thu, 24 May 2018 13:09:49 +0000 (14:09 +0100)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Thu, 28 Jun 2018 10:31:00 +0000 (11:31 +0100)
With the removal of the 32bit hypervisor build, host_pat is a constant value.
Drop the variable and the redundant cpu_has_pat predicate, and use a define
instead.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
xen/arch/x86/acpi/suspend.c
xen/arch/x86/cpu/common.c
xen/arch/x86/hvm/mtrr.c
xen/include/asm-x86/cpufeature.h
xen/include/asm-x86/processor.h

index 044bd8159438fe3734f508a2b858c6f32af3dc03..eecf357a9efe9b17dcaffa98641f956cd1d52f9d 100644 (file)
@@ -95,8 +95,7 @@ void restore_rest_processor_state(void)
     /* Reload FPU state on next FPU use. */
     stts();
 
-    if (cpu_has_pat)
-        wrmsrl(MSR_IA32_CR_PAT, host_pat);
+    wrmsrl(MSR_IA32_CR_PAT, XEN_MSR_PAT);
 
     mtrr_bp_restore();
 }
index 528aff18119e91e37ede4246f2b2373dd3af6f8e..3548b1232307787ae4ab3c21b695ae0081907d73 100644 (file)
@@ -47,12 +47,6 @@ unsigned int paddr_bits __read_mostly = 36;
 unsigned int hap_paddr_bits __read_mostly = 36;
 unsigned int vaddr_bits __read_mostly = VADDR_BITS;
 
-/*
- * Default host IA32_CR_PAT value to cover all memory types.
- * BIOS usually sets it to 0x07040600070406.
- */
-u64 host_pat = 0x050100070406;
-
 static unsigned int cleared_caps[NCAPINTS];
 static unsigned int forced_caps[NCAPINTS];
 
@@ -814,8 +808,7 @@ void cpu_init(void)
        if (opt_cpu_info)
                printk("Initializing CPU#%d\n", cpu);
 
-       if (cpu_has_pat)
-               wrmsrl(MSR_IA32_CR_PAT, host_pat);
+       wrmsrl(MSR_IA32_CR_PAT, XEN_MSR_PAT);
 
        /* Install correct page table. */
        write_ptbase(current);
index a61cc1e6dcaf9bb4acc4c3aa8c8b4cac1f7dbc55..c78e5c17ad54c531ea2eb0d713a74201b12ad1ac 100644 (file)
@@ -125,7 +125,7 @@ static int __init hvm_mtrr_pat_init(void)
     {
         for ( j = 0; j < PAT_TYPE_NUMS; j++ )
         {
-            if ( pat_cr_2_paf(host_pat, j) == i )
+            if ( pat_cr_2_paf(XEN_MSR_PAT, j) == i )
             {
                 pat_entry_tbl[i] = j;
                 break;
index 2cf8f7ea2a62cd3d1edc12ee4fe617d215b7e75a..2b1f03c70e8681ee33e725b53f9e514af8dbb7b5 100644 (file)
@@ -37,7 +37,6 @@
 #define cpu_has_sep             boot_cpu_has(X86_FEATURE_SEP)
 #define cpu_has_mtrr            1
 #define cpu_has_pge             1
-#define cpu_has_pat             1
 #define cpu_has_pse36           boot_cpu_has(X86_FEATURE_PSE36)
 #define cpu_has_clflush         boot_cpu_has(X86_FEATURE_CLFLUSH)
 #define cpu_has_mmx             1
index 9924cdf1f320b89f29fcb61e196f3563b5a909ef..ac1577c61ed2afa91f85b58a6afe993a10602e1d 100644 (file)
                           X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF|    \
                           X86_EFLAGS_TF)
 
+/*
+ * Host IA32_CR_PAT value to cover all memory types.  This is not the default
+ * MSR_PAT value, and is an ABI with PV guests.
+ */
+#define XEN_MSR_PAT 0x050100070406ul
+
 #ifndef __ASSEMBLY__
 
 struct domain;
@@ -145,7 +151,6 @@ extern bool probe_cpuid_faulting(void);
 extern void ctxt_switch_levelling(const struct vcpu *next);
 extern void (*ctxt_switch_masking)(const struct vcpu *next);
 
-extern u64 host_pat;
 extern bool_t opt_cpu_info;
 extern u32 cpuid_ext_features;
 extern u64 trampoline_misc_enable_off;