__vmwrite(HOST_GS_BASE, 0);
/* Host control registers. */
- __vmwrite(HOST_CR0, read_cr0() | X86_CR0_TS);
+ v->arch.hvm_vmx.host_cr0 = read_cr0() | X86_CR0_TS;
+ __vmwrite(HOST_CR0, v->arch.hvm_vmx.host_cr0);
__vmwrite(HOST_CR4, mmu_cr4_features);
/* Host CS:RIP. */
static void vmx_ctxt_switch_from(struct vcpu *v)
{
+ ASSERT(read_cr0() & X86_CR0_TS);
+ if ( !(v->arch.hvm_vmx.host_cr0 & X86_CR0_TS) )
+ {
+ v->arch.hvm_vmx.host_cr0 |= X86_CR0_TS;
+ __vmwrite(HOST_CR0, v->arch.hvm_vmx.host_cr0);
+ }
+
vmx_save_guest_msrs(v);
vmx_restore_host_msrs();
vmx_save_dr(v);
setup_fpu(current);
__vm_clear_bit(EXCEPTION_BITMAP, TRAP_no_device);
+ ASSERT(v->arch.hvm_vmx.host_cr0 & X86_CR0_TS);
+ v->arch.hvm_vmx.host_cr0 &= ~X86_CR0_TS;
+ __vmwrite(HOST_CR0, v->arch.hvm_vmx.host_cr0);
+
/* Disable TS in guest CR0 unless the guest wants the exception too. */
if ( !(v->arch.hvm_vcpu.guest_cr[0] & X86_CR0_TS) )
{
#ifndef __ASM_X86_HVM_VMX_CPU_H__
#define __ASM_X86_HVM_VMX_CPU_H__
-/*
- * Virtual CPU
- */
-struct arch_state_struct {
- unsigned long mode_flags; /* vm86, 32-bit, 64-bit, etc. */
- /* debug registers */
- /* MSRs */
-};
-
-#define VMX_MF_VM86 0
-#define VMX_MF_32 1
-#define VMX_MF_64 2
-
#define NUM_CORES_RESET_MASK 0x00003FFF
#define NUM_THREADS_RESET_MASK 0xFF00FFFF
unsigned int host_msr_count;
struct vmx_msr_entry *host_msr_area;
+ unsigned long host_cr0;
+
#ifdef VMXASSIST
unsigned long vmxassist_enabled:1;
unsigned long irqbase_mode:1;