X86: Disable PCID/INVPCID for dom0

PCID (Process-context identifier) is a facility by which a logical
processor may cache information for multiple linear-address spaces.
INVPCID is an new instruction to invalidate TLB. Refer latest Intel SDM
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html

We disable PCID/INVPCID for dom0 and pv. Exposing them into dom0 and pv
may result in performance regression, and it would trigger GP or UD
depending on whether platform suppport INVPCID or not.

This patch disables PCID/INVPCID for dom0.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 03dc7c3501b5d2b59c207237def828d5071a8ac7..7f38ddce6b45d0412c2e4e5d23f38362aecc28f0 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -841,6 +841,7 @@ static void pv_cpuid(struct cpu_user_regs *regs)
             __clear_bit(X86_FEATURE_CX16 % 32, &c);
         __clear_bit(X86_FEATURE_XTPR % 32, &c);
         __clear_bit(X86_FEATURE_PDCM % 32, &c);
+        __clear_bit(X86_FEATURE_PCID % 32, &c);
         __clear_bit(X86_FEATURE_DCA % 32, &c);
         if ( !xsave_enabled(current) )
         {

diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 776333a75f39ae0888ab1e8e62dc5d6b537bb24f..c98b7569bf2081fd59fd0169cc263399731abfa0 100644 (file)
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -97,6 +97,7 @@
 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR       (4*32+14) /* Send Task Priority Messages */
 #define X86_FEATURE_PDCM       (4*32+15) /* Perf/Debug Capability MSR */
+#define X86_FEATURE_PCID       (4*32+17) /* Process Context ID */
 #define X86_FEATURE_DCA                (4*32+18) /* Direct Cache Access */
 #define X86_FEATURE_SSE4_1     (4*32+19) /* Streaming SIMD Extensions 4.1 */
 #define X86_FEATURE_SSE4_2     (4*32+20) /* Streaming SIMD Extensions 4.2 */
@@ -152,6 +153,7 @@
 #define X86_FEATURE_SMEP       (7*32+ 7) /* Supervisor Mode Execution Protection */
 #define X86_FEATURE_BMI2       (7*32+ 8) /* 2nd bit manipulation extensions */
 #define X86_FEATURE_ERMS       (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
+#define X86_FEATURE_INVPCID    (7*32+10) /* Invalidate Process Context ID */
 
 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)