x86: allow Dom0 to control a few more MSR bits

Linux 2.6.27 adds code to enable extended config space accesses in the
Northbridge Configuration MSR; Xen should allow Dom0 to control the
respective bit.

Likewise, 2.6.26 added support to enable the MMIO config space access
method for certain Sun systems, so similarly Xen should allow Dom0 to
control the respective fields of the MMIO Configuration Base Address
Register.

Signed-off-by: Jan Beulich <jbeulich@novell.com>

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 1b65a9bb9d89c84c754ff8159a8bcddf09f14220..75b9e44be3b45febe01c71438301cd28678182c6 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2116,6 +2116,36 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
             if ( wrmsr_safe(regs->ecx, eax, edx) != 0 )
                 goto fail;
             break;
+        case MSR_AMD64_NB_CFG:
+            if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+                 boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
+                goto fail;
+            if ( !IS_PRIV(v->domain) )
+                break;
+            if ( (rdmsr_safe(MSR_AMD64_NB_CFG, l, h) != 0) ||
+                 (eax != l) ||
+                 ((edx ^ h) & ~(1 << (AMD64_NB_CFG_CF8_EXT_ENABLE_BIT - 32))) )
+                goto invalid;
+            if ( wrmsr_safe(MSR_AMD64_NB_CFG, eax, edx) != 0 )
+                goto fail;
+            break;
+        case MSR_FAM10H_MMIO_CONF_BASE:
+            if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
+                 boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
+                goto fail;
+            if ( !IS_PRIV(v->domain) )
+                break;
+            if ( (rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, l, h) != 0) ||
+                 (((((u64)h << 32) | l) ^ res) &
+                  ~((1 << FAM10H_MMIO_CONF_ENABLE_BIT) |
+                    (FAM10H_MMIO_CONF_BUSRANGE_MASK <<
+                     FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
+                    ((u64)FAM10H_MMIO_CONF_BASE_MASK <<
+                     FAM10H_MMIO_CONF_BASE_SHIFT))) )
+                goto invalid;
+            if ( wrmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, eax, edx) != 0 )
+                goto fail;
+            break;
         case MSR_IA32_PERF_CTL:
             if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
                 goto fail;
@@ -2129,6 +2159,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
                 break;
             if ( (rdmsr_safe(regs->ecx, l, h) != 0) ||
                  (eax != l) || (edx != h) )
+        invalid:
                 gdprintk(XENLOG_WARNING, "Domain attempted WRMSR %p from "
                         "%08x:%08x to %08x:%08x.\n",
                         _p(regs->ecx), h, l, edx, eax);

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index b49baf2f1abe182a2b2fff33fe20fd54d3bd391e..08079bc5cd50e81af1076759d6fc29b4a2ed13b7 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -194,11 +194,23 @@
 #define _K8_VMCR_SVME_DISABLE          4
 #define K8_VMCR_SVME_DISABLE           (1 << _K8_VMCR_SVME_DISABLE)
 
+/* AMD64 MSRs */
+#define MSR_AMD64_NB_CFG               0xc001001f
+#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT        46
+
 /* AMD Family10h machine check MSRs */
 #define MSR_F10_MC4_MISC1              0xc0000408
 #define MSR_F10_MC4_MISC2              0xc0000409
 #define MSR_F10_MC4_MISC3              0xc000040A
 
+/* Other AMD Fam10h MSRs */
+#define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
+#define FAM10H_MMIO_CONF_ENABLE_BIT    0
+#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
+#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
+#define FAM10H_MMIO_CONF_BASE_MASK     0xfffffff
+#define FAM10H_MMIO_CONF_BASE_SHIFT    20
+
 /* K6 MSRs */
 #define MSR_K6_EFER                    0xc0000080
 #define MSR_K6_STAR                    0xc0000081