This wasn't done properly by
4d66f069 ("x86: fix pinned cache attribute
handling"): The passed in GFN shouldn't be assumed to be order aligned.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Tim Deegan <tim@xen.org>
uint32_t *type)
{
struct hvm_mem_pinned_cacheattr_range *range;
+ uint64_t mask = ~(uint64_t)0 << order;
int rc = 0;
*type = ~0;
&d->arch.hvm_domain.pinned_cacheattr_ranges,
list )
{
- if ( (guest_fn >= range->start) &&
- (guest_fn + (1UL << order) - 1 <= range->end) )
+ if ( ((guest_fn & mask) >= range->start) &&
+ ((guest_fn | ~mask) <= range->end) )
{
*type = range->type;
rc = 1;
break;
}
- if ( (guest_fn <= range->end) &&
- (range->start <= guest_fn + (1UL << order) - 1) )
+ if ( ((guest_fn & mask) <= range->end) &&
+ (range->start <= (guest_fn | ~mask)) )
{
rc = -1;
break;