--- /dev/null
+---
+BasedOnStyle: Google
+DerivePointerAlignment: false
+PointerAlignment: Left
+ColumnLimit: 80
+AlignAfterOpenBracket: Align
+AlignEscapedNewlines: Right
+AlignTrailingComments: true
--- /dev/null
+*~
+build
+GPATH
+GTAGS
+GRTAGS
+#*#
+.#*
+*.swp
--- /dev/null
+before_script:
+ - echo start testing $CI_PROJECT_NAME.
+ - git clone gits@xcdl190260:aisw/unilog
+
+build_on_host:
+ tags:
+ - aisw
+ script:
+ - source /opt/rh/devtoolset-9/enable
+ - (cd unilog; ./cmake.sh --clean)
+ - ./cmake.sh --clean
+
+build_for_microblaze:
+ tags:
+ - aisw
+ script:
+ - source /var/lib/docker/scratch/gitlab-runner/build/mb_sdk/environment-setup-microblazeel-v11.0-bs-cmp-re-mh-div-xilinx-linux
+ - (cd unilog; ./cmake.sh --clean)
+ - ./cmake.sh --clean
+
+build_for_petalinux:
+ tags:
+ - aisw
+ script:
+ - source /var/lib/docker/scratch/gitlab-runner/build/sdk-0618/environment-setup-aarch64-xilinx-linux
+ - (cd unilog; ./cmake.sh --clean)
+ - ./cmake.sh --clean
--- /dev/null
+#
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+cmake_minimum_required(VERSION 3.5)
+project(target-factory VERSION 2.5.0 LANGUAGES C CXX)
+
+include(${PROJECT_SOURCE_DIR}/cmake/VitisCommon.cmake)
+
+option(BUILD_TEST "build test" OFF)
+
+find_package(glog)
+find_package(Protobuf REQUIRED)
+if(NOT TARGET unilog::unilog)
+ find_package(unilog REQUIRED)
+endif()
+
+add_subdirectory(src)
+
+file(RELATIVE_PATH REL_INCLUDE_DIR
+ ${CMAKE_INSTALL_PREFIX}/share/cmake/${PROJECT_NAME}
+ ${CMAKE_INSTALL_PREFIX}/include)
+
+set(CONF_INCLUDE_DIRS "\${${PROJECT_NAME}_CMAKE_DIR}/${REL_INCLUDE_DIR}")
+configure_file(cmake/config.cmake.in
+ "${CMAKE_BINARY_DIR}/${PROJECT_NAME}-config.cmake"
+ @ONLY)
+
+write_basic_package_version_file(
+ "${CMAKE_BINARY_DIR}/${PROJECT_NAME}-config-version.cmake"
+ VERSION ${PROJECT_VERSION}
+ COMPATIBILITY AnyNewerVersion)
+
+install(FILES
+ "${CMAKE_BINARY_DIR}/${PROJECT_NAME}-config.cmake"
+ "${CMAKE_BINARY_DIR}/${PROJECT_NAME}-config-version.cmake"
+ DESTINATION share/cmake/${PROJECT_NAME})
+
+if(BUILD_TEST)
+ add_subdirectory(test)
+endif()
+
+set(CPACK_PACKAGE_NAME "libtarget-factory")
+set(CPACK_PACKAGE_DESCRIPTION_SUMMARY "A factory to generate DPU target description file")
+set(CPACK_PACKAGE_DESCRIPTION_FILE "${PROJECT_SOURCE_DIR}/README.md")
+set(CPACK_RESOURCE_FILE_README "${PROJECT_SOURCE_DIR}/README.md")
+set(CPACK_RESOURCE_FILE_LICENSE "${PROJECT_SOURCE_DIR}/Copyright.txt")
+set(CPACK_PACKAGE_VENDOR "Humanity")
+set(CPACK_PACKAGE_VERSION_MAJOR ${CMAKE_PROJECT_VERSION_MAJOR})
+set(CPACK_PACKAGE_VERSION_MINOR ${CMAKE_PROJECT_VERSION_MINOR})
+set(CPACK_PACKAGE_VERSION_PATCH ${CMAKE_PROJECT_VERSION_PATCH})
+set(CPACK_PACKAGE_CONTACT "Jian Weng<jianweng@xilinx.com>")
+set(CPACK_PACKAGING_INSTALL_PREFIX "/usr")
+
+set(CPACK_DEB_COMPONENT_INSTALL OFF)
+set(CPACK_DEBIAN_PACKAGE_SECTION "devel")
+set(CPACK_DEBIAN_ARCHIVE_TYPE "gnutar")
+set(CPACK_DEBIAN_COMPRESSION_TYPE "gzip")
+set(CPACK_DEBIAN_PACKAGE_PRIORITY "optional")
+set(CPACK_DEBIAN_PACKAGE_DEPENDS "libunilog (>=1.2.0)")
+set(CPACK_DEBIAN_FILE_NAME DEB-DEFAULT)
+if(DEFINED ENV{BUILD_NUMBER})
+ set(CPACK_DEBIAN_PACKAGE_RELEASE "r$ENV{BUILD_NUMBER}")
+endif()
+if(CMAKE_SYSTEM_PROCESSOR STREQUAL "aarch64")
+ set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE "arm64")
+elseif(CMAKE_SYSTEM_PROCESSOR STREQUAL "x86_64")
+ set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE "amd64")
+else()
+ set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE ${CMAKE_SYSTEM_PROCESSOR})
+endif()
+
+set(CPACK_RPM_COMPONENT_INSTALL OFF)
+set(CPACK_RPM_PACKAGE_LICENSE "Apache")
+set(CPACK_RPM_PACKAGE_GROUP "Development/Tools")
+set(CPACK_RPM_COMPRESSION_TYPE "xz")
+set(CPACK_RPM_PACKAGE_REQUIRES "libunilog >= 1.2.0")
+set(CPACK_RPM_FILE_NAME RPM-DEFAULT)
+if(DEFINED ENV{BUILD_NUMBER})
+ set(CPACK_RPM_PACKAGE_RELEASE "r$ENV{BUILD_NUMBER}")
+endif()
+set(CPACK_RPM_PACKAGE_ARCHITECTURE ${CMAKE_SYSTEM_PROCESSOR})
+if(CMAKE_SYSTEM_PROCESSOR STREQUAL "cortexa72-cortexa53")
+ set(CPACK_RPM_PACKAGE_ARCHITECTURE "aarch64")
+endif()
+
+include(CPack)
--- /dev/null
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
--- /dev/null
+A factory to manage DPU target description infos. Register targets and then you can get infos by name or fingerprint.
--- /dev/null
+@ECHO OFF
+
+SET PREFIX=C:\Xilinx\XRT\ext
+
+IF "%1" == "-clean" (
+ GOTO Clean
+)
+
+IF "%1" == "-help" (
+ GOTO Help
+)
+
+IF "%1" == "-debug" (
+ GOTO DebugBuild
+)
+
+IF "%1" == "-release" (
+ GOTO ReleaseBuild
+)
+
+IF "%1" == "-all" (
+ CALL:DebugBuild
+ IF errorlevel 1 (exit /B %errorlevel%)
+
+ CALL:ReleaseBuild
+ IF errorlevel 1 (exit /B %errorlevel%)
+
+ goto:EOF
+)
+
+IF "%1" == "" (
+
+ CALL:ReleaseBuild
+ IF errorlevel 1 (exit /B %errorlevel%)
+
+ GOTO:EOF
+)
+
+ECHO Unknown option: %1
+GOTO Help
+
+
+REM --------------------------------------------------------------------------
+:Help
+ECHO.
+ECHO Usage: build.bat [options]
+ECHO.
+ECHO [-help] - List this help
+ECHO [-clean] - Remove build directories
+ECHO [-debug] - Creates a debug build
+ECHO [-release] - Creates a release build
+ECHO [-all] - Creates a release build and a debug build
+ECHO.
+GOTO:EOF
+
+REM --------------------------------------------------------------------------
+:Clean
+IF EXIST WDebug (
+ ECHO Removing 'WDebug' directory...
+ rmdir /S /Q WDebug
+)
+IF EXIST WRelease (
+ ECHO Removing 'WRelease' directory...
+ rmdir /S /Q WRelease
+)
+GOTO:EOF
+
+REM --------------------------------------------------------------------------
+:DebugBuild
+ECHO ====================== Windows Debug Build ============================
+MKDIR WDebug
+PUSHD WDebug
+
+cmake -G "Visual Studio 15 2017 Win64" -DCMAKE_PREFIX_PATH=%PREFIX% -DCMAKE_INSTALL_PREFIX=%PREFIX% -DCMAKE_BUILD_TYPE=Debug -DCMAKE_EXPORT_COMPILE_COMMANDS=ON ..
+IF errorlevel 1 (POPD & exit /B %errorlevel%)
+
+cmake --build . --verbose --config Debug
+IF errorlevel 1 (POPD & exit /B %errorlevel%)
+
+cmake --build . --verbose --config Debug --target install
+IF errorlevel 1 (POPD & exit /B %errorlevel%)
+
+ECHO ====================== Zipping up Installation Build ============================
+cpack -G ZIP -C Debug
+
+ECHO ====================== Creating MSI Archive ============================
+cpack -G WIX -C Debug
+
+POPD
+GOTO:EOF
+
+REM --------------------------------------------------------------------------
+:ReleaseBuild
+ECHO ====================== Windows Release Build ============================
+MKDIR WRelease
+PUSHD WRelease
+
+cmake -G "Visual Studio 15 2017 Win64" -DCMAKE_PREFIX_PATH=%PREFIX% -DCMAKE_INSTALL_PREFIX=%PREFIX% -DCMAKE_BUILD_TYPE=Release -DCMAKE_EXPORT_COMPILE_COMMANDS=ON ..
+IF errorlevel 1 (POPD & exit /B %errorlevel%)
+
+cmake --build . --verbose --config Release
+IF errorlevel 1 (POPD & exit /B %errorlevel%)
+
+cmake --build . --verbose --config Release --target install
+IF errorlevel 1 (POPD & exit /B %errorlevel%)
+
+ECHO ====================== Zipping up Installation Build ============================
+cpack -G ZIP -C Release
+
+ECHO ====================== Creating MSI Archive ============================
+cpack -G WIX -C Release
+
+POPD
+GOTO:EOF
+
+
--- /dev/null
+#!/bin/bash
+
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set -e
+
+script_path=$(dirname "$(realpath $0)")
+project_name=$(basename ${script_path})
+
+# cmake args
+declare -a args
+args=(-DBUILD_TEST=ON)
+
+# parse options
+options=$(getopt -a -n 'parse-options' -o h \
+ -l help,conda,clean,build-only,type:,pack:,build-dir:,install-prefix:,cmake-options: \
+ -- "$0" "$@")
+[ $? -eq 0 ] || {
+ echo "Failed to parse arguments! try --help"
+ exit 1
+}
+eval set -- "$options"
+while true; do
+ case "$1" in
+ -h | --help) show_help=true; break;;
+ --clean) clean=true;;
+ --conda) conda=true;;
+ --build-only) build_only=true;;
+ --type)
+ shift
+ case "$1" in
+ release) build_type=Release;;
+ debug) build_type=Debug;;
+ *) echo "Invalid build type \"$1\"! try --help"; exit 1;;
+ esac
+ ;;
+ --pack)
+ shift
+ build_package=true
+ case "$1" in
+ deb) args+=(-DCPACK_GENERATOR="DEB");;
+ rpm) args+=(-DCPACK_GENERATOR="RPM");;
+ *) echo "Invalid pack format \"$1\"! try --help"; exit 1;;
+ esac
+ ;;
+ --build-dir) shift; build_dir=$1;;
+ --install-prefix) shift; install_prefix=$1;;
+ --cmake-options) shift; args+=($1);;
+ --) shift; break;;
+ esac
+ shift
+done
+
+# conda
+if [ ${conda:=false} == true ]; then
+ args+=(-DCMAKE_PREFIX_PATH=${CONDA_PREFIX})
+fi
+
+# set build type
+args+=(-DCMAKE_BUILD_TYPE=${build_type:="Debug"})
+[ ${build_type} == "Debug" ] && args+=(-DCMAKE_EXPORT_COMPILE_COMMANDS=ON)
+
+# detect target & set install prefix
+if [ -z ${OECORE_TARGET_SYSROOT:+x} ]; then
+ echo "Native-platform building..."
+ os=`lsb_release -a | grep "Distributor ID" | sed 's/^.*:\s*//'`
+ os_version=`lsb_release -a | grep "Release" | sed 's/^.*:\s*//'`
+ arch=`uname -p`
+ target_info=${os}.${os_version}.${arch}.${build_type}
+ install_prefix_default=$HOME/.local/${target_info}
+else
+ echo "Cross-platform building..."
+ echo "Found target sysroot ${OECORE_TARGET_SYSROOT}"
+ target_info=${OECORE_TARGET_OS}.${OECORE_SDK_VERSION}.${OECORE_TARGET_ARCH}.${build_type}
+ install_prefix=${OECORE_TARGET_SYSROOT}/install/${build_type}
+ args+=(-DCMAKE_TOOLCHAIN_FILE=${OECORE_NATIVE_SYSROOT}/usr/share/cmake/OEToolchainConfig.cmake)
+ args+=(-DCMAKE_PREFIX_PATH=/install/${build_type})
+fi
+args+=(-DCMAKE_INSTALL_PREFIX=${install_prefix:="${install_prefix_default}"})
+
+# set build dir
+build_dir_default=$HOME/build/build.${target_info}/${project_name}
+[ -z ${build_dir:+x} ] && build_dir=${build_dir_default}
+
+if [ ${show_help:=false} == true ]; then
+ echo "./cmake.sh [options]"
+ echo " --help show help"
+ echo " --clean discard build dir before build"
+ echo " --build-only build only, will not install"
+ echo " --type[=TYPE] build type. VAR {release, debug(default)}"
+ echo " --pack[=FORMAT] enable packing and set package format. VAR {deb, rpm}"
+ echo " --build-dir[=DIR] set customized build directory. default directory is ${build_dir_default}"
+ echo " --install-prefix[=PREFIX] set customized install prefix. default prefix is ${install_prefix_default}"
+ echo " --cmake-options[=OPTIONS] append more cmake options"
+else
+ mkdir -p ${build_dir}
+ ${clean:=false} && rm -fr ${build_dir}/*
+ cd -P ${build_dir}
+ echo "cd $PWD"
+ echo cmake "${args[@]}" "$script_path"
+ cmake "${args[@]}" "$script_path"
+ make -j $(nproc)
+ ${build_only:=false} || make install
+ ${build_package:=false} && make package
+fi
+
+exit 0
--- /dev/null
+#
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+set (CMAKE_CXX_STANDARD 14)
+set (CMAKE_C_STANDARD 99)
+#set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -Wl,--no-undefined")
+
+if(CMAKE_BUILD_TYPE MATCHES "Release")
+ ADD_DEFINITIONS(-DUNI_LOG_NDEBUG)
+endif()
+if(NOT MSVC)
+ set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -Wall -Werror -ggdb -O0 -fno-inline")
+ set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -O3 -Wall -Werror")
+ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=gnu++14 -Wall -Werror")
+ set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -Werror")
+ set(CMAKE_EXE "${CMAKE_C_FLAGS} -Wall -Werror")
+ set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -Wl,--no-undefined")
+
+ set(CMAKE_MACOSX_RPATH 1)
+endif(NOT MSVC)
+
+include(CMakePackageConfigHelpers)
+
+if(NOT CMAKE_CROSSCOMPILING)
+ set(CMAKE_INSTALL_RPATH_USE_LINK_PATH True)
+endif()
--- /dev/null
+#
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+include("${CMAKE_CURRENT_LIST_DIR}/@PROJECT_NAME@-targets.cmake")
+set(@PROJECT_NAME@_FOUND True)
+
+get_target_property(TARGET_LOCATION @PROJECT_NAME@::@PROJECT_NAME@ LOCATION)
+message(STATUS "Found importable target @PROJECT_NAME@::@PROJECT_NAME@: ${TARGET_LOCATION}")
+
+get_filename_component(@PROJECT_NAME@_CMAKE_DIR "${CMAKE_CURRENT_LIST_FILE}" PATH)
+set(@PROJECT_NAME@_INCLUDE_DIRS "@CONF_INCLUDE_DIRS@")
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B16384C64B1"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x000076080812
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 64
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+batch: 1
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B16384C64B1_DW"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x0000f6088812
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 64
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+dwconv_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+batch: 1
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B4096C16B1_DW_QT"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x0004f2022210
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+dwconv_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+batch: 1
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B4096C16B3_DW"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x0000f6088830
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+dwconv_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B8192C32B1"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x000076080811
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+batch: 1
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B8192C32B1_ELP4"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x000076040411
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+batch: 1
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B8192C32B3"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x000076080831
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B8192C32B3_ALU"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x0130f6088831
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-8"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B8192C32B3_DW"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x0000f6088831
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+dwconv_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B8192C32B3_I4W8B2"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x000276080831
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B8192C32B3_I8W4B2"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x000376080831
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA0_B8192C32B3_I8W8B2"
+type: "DPUCVDX8G"
+isa_version: 0x00
+feature_code: 0x000176080831
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA1_C16B1_QT"
+type: "DPUCVDX8G"
+isa_version: 0x01
+feature_code: 0x001432022110
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 4096
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-8"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 1
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA1_C32B3"
+type: "DPUCVDX8G"
+isa_version: 0x01
+feature_code: 0x001036088131
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-8"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA2_C32B3"
+type: "DPUCVDX8G"
+isa_version: 0x02
+feature_code: 0x001036088231
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8H_ISA0"
+type: "DPUCVDX8H"
+isa_version: 0x00
+feature_code: 0x7ee
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 128
+ bank_width: 64
+ bank_depth: 256
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 144
+ bank_num: 1
+ bank_width: 128
+ bank_depth: 1024
+}
+load_engine {
+ channel_parallel: 64
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 128
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 64
+ output_channel_parallel: 128
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 64
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ conv_cascade {
+ pixel_parallel: 8
+ }
+}
+pool_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-3,7"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "1-3,7"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8H_ISA0_1STLAYER"
+type: "DPUCVDX8H"
+isa_version: 0x00
+feature_code: 0x436
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 128
+ bank_width: 64
+ bank_depth: 256
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 144
+ bank_num: 1
+ bank_width: 128
+ bank_depth: 32
+}
+load_engine {
+ channel_parallel: 64
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 128
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 64
+ output_channel_parallel: 128
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 64
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ conv_cascade {
+ pixel_parallel: 8
+ }
+}
+pool_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-3,7"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "1-3,7"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8H_ISA0_6PE"
+type: "DPUCVDX8H"
+isa_version: 0x00
+feature_code: 0x42e
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 128
+ bank_width: 64
+ bank_depth: 256
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 144
+ bank_num: 1
+ bank_width: 128
+ bank_depth: 1024
+}
+load_engine {
+ channel_parallel: 64
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 128
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 64
+ output_channel_parallel: 128
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 64
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ conv_cascade {
+ pixel_parallel: 8
+ }
+}
+pool_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B1024_MAX"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f7014402
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 16
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 8
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+}
+save_engine {
+ channel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 8
+ output_channel_parallel: 8
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 16
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 8
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 8
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 8
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B1024_MIN"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x002022010102
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 24
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 8
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 8
+ output_channel_parallel: 8
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 8
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 8
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B1152_MAX"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f7012203
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 4
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 12
+ bank_num: 12
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 25
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 12
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+}
+save_engine {
+ channel_parallel: 12
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 12
+ output_channel_parallel: 12
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 24
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 12
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 12
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 12
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B1152_MIN"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x002022010103
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 8
+ bank_num: 12
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 20
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 12
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 12
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 12
+ output_channel_parallel: 12
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 12
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 12
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B1600_MAX"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f7014404
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 16
+ bank_num: 8
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 10
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 35
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 10
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+}
+save_engine {
+ channel_parallel: 10
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 10
+ output_channel_parallel: 10
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 20
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 10
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 10
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 10
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B1600_MIN"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x002022010104
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 10
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 26
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 10
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 10
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 10
+ output_channel_parallel: 10
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 10
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 10
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B2304_MAX"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f7014405
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 16
+ bank_num: 8
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 12
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 36
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 37
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 12
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+}
+save_engine {
+ channel_parallel: 12
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 12
+ output_channel_parallel: 12
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 24
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 12
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 12
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 12
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B2304_MAX_BG2"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f6014405
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 12
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 28
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 29
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 12
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 12
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 12
+ output_channel_parallel: 12
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 24
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 12
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 12
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 12
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B2304_MIN"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x002022010105
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 12
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 28
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 12
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 12
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 12
+ output_channel_parallel: 12
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 12
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 12
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B3136_MAX"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f7014406
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 16
+ bank_num: 8
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 14
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 38
+ bank_num: 1
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 39
+ bank_num: 1
+ bank_width: 14
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 14
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+}
+save_engine {
+ channel_parallel: 14
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 14
+ output_channel_parallel: 14
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 28
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 14
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 14
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 14
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B3136_MAX_BG2"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f6014406
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 14
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 30
+ bank_num: 1
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 31
+ bank_num: 1
+ bank_width: 14
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 14
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 14
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 14
+ output_channel_parallel: 14
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 28
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 14
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 14
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 14
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B3136_MIN"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x002022010106
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 14
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 30
+ bank_num: 1
+ bank_width: 14
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 14
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 14
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 14
+ output_channel_parallel: 14
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 14
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 14
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B4096_MAX"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f7014407
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 16
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 40
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 41
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B4096_MAX_BG2"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f6014407
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B4096_MAX_EM"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0030f7014407
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 16
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 40
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 41
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B4096_MIN"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x002022010107
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B512_MAX"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f7012200
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 4
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 12
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 20
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 21
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 8
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+}
+save_engine {
+ channel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 8
+ output_channel_parallel: 8
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 16
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 8
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 8
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 8
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B512_MIN"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x002022010100
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 8
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 16
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 8
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 8
+ output_channel_parallel: 8
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 8
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 8
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B800_MAX"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x0020f7012201
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 4
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 12
+ bank_num: 10
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 22
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 23
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 10
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+}
+save_engine {
+ channel_parallel: 10
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 10
+ output_channel_parallel: 10
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 20
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 10
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 10
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "2-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
+dwconv_engine {
+ channel_parallel: 10
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA0_B800_MIN"
+type: "DPUCZDX8G"
+isa_version: 0x00
+feature_code: 0x002022010101
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 8
+ bank_num: 10
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 18
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 10
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 10
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 10
+ output_channel_parallel: 10
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 10
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 10
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ pool_type: max_reduce
+}
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#pragma once
+#if defined(_WIN32)
+ #ifdef TARGET_FACTORY_EXPORT
+ #define TARGET_FACTORY_DLLESPEC __declspec(dllexport)
+ #else
+ #define TARGET_FACTORY_DLLESPEC __declspec(dllimport)
+ #endif
+#else
+ #define TARGET_FACTORY_DLLESPEC __attribute__((visibility("default")))
+#endif
+
+#include <string>
+
+#include "target.pb.h"
+
+namespace vitis {
+namespace ai {
+
+class TARGET_FACTORY_DLLESPEC TargetFactory {
+ public:
+ virtual const Target create(const std::string& name) const = 0;
+ virtual const Target create(const std::uint64_t fingerprint) const = 0;
+ virtual const Target create(const std::string& type,
+ std::uint64_t isa_version,
+ std::uint64_t feature_code) const = 0;
+
+ virtual const std::uint64_t get_fingerprint(
+ const std::string& name) const = 0;
+ virtual const std::uint64_t get_fingerprint(
+ const std::string& type, std::uint64_t isa_version,
+ std::uint64_t feature_code) const = 0;
+
+ virtual void dump(const Target& target, const std::string& file) const = 0;
+ virtual bool is_registered_target(const std::string& name) const = 0;
+ static const std::string get_lib_name();
+ static const std::string get_lib_id();
+
+ public:
+ virtual ~TargetFactory() = default;
+};
+
+TARGET_FACTORY_DLLESPEC
+const TargetFactory* target_factory();
+
+} // namespace ai
+} // namespace vitis
--- /dev/null
+# This file may be used to create an environment using:
+# $ conda create --name <env> --file <this file>
+# platform: linux-64
+cmake=3.16.0=h28c56e5_2
+pybind11=2.3.0=py36hc9558a2_2
+libprotobuf=3.11.4=h8b12597_0
--- /dev/null
+#Copyright 2019 Xilinx Inc.
+#
+#Licensed under the Apache License, Version 2.0(the "License");
+#you may not use this file except in compliance with the License.
+#You may obtain a copy of the License at
+#
+#http: // www.apache.org/licenses/LICENSE-2.0
+#
+#Unless required by applicable law or agreed to in writing, software
+#distributed under the License is distributed on an "AS IS" BASIS,
+#WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#See the License for the specific language governing permissions and
+#limitations under the License.
+
+import os
+import subprocess
+import sys
+import shutil
+
+from setuptools import Extension, setup, find_packages
+from setuptools.command.build_ext import build_ext
+
+def get_shell_result(shell_cmd):
+ proc = subprocess.Popen(shell_cmd, stdout=subprocess.PIPE, shell=True)
+ outs, _ = proc.communicate(timeout=2)
+ res = outs.strip().decode("utf-8")
+ return res
+
+class CMakeExtension(Extension):
+
+ def __init__(self, name, sourcedir=""):
+ Extension.__init__(self, name, sources=[])
+ self.sourcedir = os.path.abspath(sourcedir)
+
+
+class CMakeBuild(build_ext):
+
+ def build_extension(self, ext):
+ extdir = os.path.abspath(os.path.dirname(self.get_ext_fullpath(ext.name)))
+ _os = get_shell_result("lsb_release -a | grep 'Distributor ID'| sed 's/^.*:\s*//'")
+ os_version = get_shell_result("lsb_release -a | grep 'Release' | sed 's/^.*:\s*//'")
+ arch = get_shell_result("uname -p")
+ target_info = f"{_os}.{os_version}.{arch}.Debug"
+ home = os.environ.get("HOME")
+ install_prefix_default = f"{home}/.local/{target_info}"
+
+
+ cmake_args = [
+ f"-DCMAKE_LIBRARY_OUTPUT_DIRECTORY={extdir}",
+ f"-DBUILD_PYTHON=ON",
+ f"-DCMAKE_BUILD_TYPE=Debug",
+ f"-DPYTHON_EXECUTABLE={sys.executable}",
+ f"-DCMAKE_EXPORT_COMPILE_COMMANDS=ON",
+ f"-DCMAKE_INSTALL_PREFIX={install_prefix_default}"
+ ]
+ cwd = os.getcwd()
+ if not os.path.exists(extdir):
+ os.makedirs(extdir)
+ os.chdir(extdir)
+ subprocess.check_call(["cmake", ext.sourcedir] + cmake_args)
+ subprocess.check_call(["cmake", "--build", extdir])
+ os.chdir(cwd)
+
+def clean_install_info():
+ try:
+ for dir_name in ["dist", "target_factory.egg-info"]:
+ if os.path.exists(dir_name):
+ shutil.rmtree(dir_name)
+ except Exception:
+ print("Faile to do the cleaning, please clean up manually")
+
+
+
+setup(
+ name="target_factory",
+ version="0.0.1",
+ author="Xilinx",
+ description="Target factory using pybind11 and CMake",
+ packages=find_packages(),
+ ext_modules=[CMakeExtension("target_factory")],
+ cmdclass={"build_ext": CMakeBuild},
+ zip_safe=False,
+ python_requires=">=3.6",
+)
+
+clean_install_info()
--- /dev/null
+#
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# get the git repo branch and commit id and write them into config.hpp
+execute_process(
+ COMMAND git rev-parse --abbrev-ref HEAD
+ WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
+ OUTPUT_VARIABLE PROJECT_GIT_BRANCH_NAME
+ OUTPUT_STRIP_TRAILING_WHITESPACE)
+execute_process(
+ COMMAND git rev-parse HEAD
+ WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
+ OUTPUT_VARIABLE PROJECT_GIT_COMMIT_ID
+ OUTPUT_STRIP_TRAILING_WHITESPACE)
+configure_file(config.hpp.in config.hpp @ONLY)
+
+# run protoc
+protobuf_generate_cpp(PROTO_SRCS PROTO_HDRS EXPORT_MACRO TARGET_FACTORY_DLLESPEC target.proto)
+#set_source_files_properties(${PROTO_SRCS} PROPERTIES COMPILE_FLAGS -Wno-unused-variable)
+if(MSVC)
+ set_source_files_properties(${PROTO_SRCS} PROPERTIES COMPILE_DEFINITIONS "TARGET_FACTORY_DLLESPEC=__declspec(dllexport)")
+else(MSVC)
+ set_source_files_properties(${PROTO_SRCS} PROPERTIES COMPILE_DEFINITIONS "TARGET_FACTORY_DLLESPEC=__attribute__((visibility(\"default\")))")
+endif(MSVC)
+# process target files
+file(GLOB PROTOTXT_FILE_LIST ${PROJECT_SOURCE_DIR}/targets/*.prototxt)
+set(TARGET_PROTOTXT_LST "")
+set(TARGET_PROTOTXT_CODE "")
+foreach(PROTOTXT_FILE ${PROTOTXT_FILE_LIST})
+ file(READ ${PROTOTXT_FILE} _hex HEX)
+ # Separate into individual bytes.
+ string(REGEX MATCHALL "([A-Za-z0-9][A-Za-z0-9])" _separated_hex "${_hex}")
+ list(APPEND _separated_hex "00")
+ # Append the "0x" to each byte.
+ list(JOIN _separated_hex ",0x" _formatted_hex)
+ # JOIN misses the first byte's "0x", so add it here.
+ string(PREPEND _formatted_hex "0x")
+ string(MAKE_C_IDENTIFIER ${PROTOTXT_FILE} _c_name)
+ string(APPEND TARGET_PROTOTXT_CODE "static constexpr char ${_c_name} [] = { ${_formatted_hex} };\n")
+ list(APPEND TARGET_PROTOTXT_LST "(const char *)${_c_name}")
+endforeach()
+list(JOIN TARGET_PROTOTXT_LST "," TARGET_PROTOTXTS)
+configure_file(${PROJECT_SOURCE_DIR}/src/target_list.hpp.in target_list.hpp
+ ESCAPE_QUOTES @ONLY)
+
+# build library
+aux_source_directory(. CPP_SRCS)
+add_library(${PROJECT_NAME} SHARED ${PROTO_SRCS} ${CPP_SRCS})
+# Enable Export of public APIs
+target_compile_definitions(${PROJECT_NAME} PRIVATE -DTARGET_FACTORY_EXPORT
+ # for an unknown reason, g++ 9.3 produces compilation errors related to PRI64X
+ -D__STDC_FORMAT_MACROS=1)
+
+set_target_properties(${PROJECT_NAME} PROPERTIES
+ VERSION "${PROJECT_VERSION}"
+ SOVERSION "${PROJECT_VERSION_MAJOR}")
+target_include_directories(${PROJECT_NAME} PUBLIC
+ $<BUILD_INTERFACE:${PROJECT_SOURCE_DIR}/include>
+ $<BUILD_INTERFACE:${CMAKE_CURRENT_BINARY_DIR}>
+ $<INSTALL_INTERFACE:include>
+)
+target_link_libraries(${PROJECT_NAME} PUBLIC protobuf::libprotobuf PRIVATE unilog::unilog)
+
+# add python api
+if(BUILD_PYTHON)
+ add_subdirectory(python_api)
+endif()
+
+install(
+ TARGETS ${PROJECT_NAME}
+ EXPORT ${PROJECT_NAME}-targets
+ RUNTIME DESTINATION bin
+ ARCHIVE DESTINATION lib
+ LIBRARY DESTINATION lib)
+install(
+ FILES ${PROTO_HDRS} ${PROJECT_SOURCE_DIR}/include/vitis/ai/target_factory.hpp
+ DESTINATION include/vitis/ai)
+install(
+ EXPORT ${PROJECT_NAME}-targets
+ NAMESPACE ${PROJECT_NAME}::
+ DESTINATION share/cmake/${PROJECT_NAME})
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#pragma once
+
+#cmakedefine PROJECT_NAME "@PROJECT_NAME@"
+#cmakedefine PROJECT_VERSION "@PROJECT_VERSION@"
+
+#cmakedefine PROJECT_GIT_BRANCH_NAME "@PROJECT_GIT_BRANCH_NAME@"
+#cmakedefine PROJECT_GIT_COMMIT_ID "@PROJECT_GIT_COMMIT_ID@"
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include <inttypes.h>
+#include <array>
+#include "vitis/ai/target_factory.hpp"
+
+namespace vitis {
+namespace ai {
+
+const Target create_target_DPUCVDX8G_ISA2(const std::uint64_t fingerprint) {
+ Target target;
+ target.set_type("DPUCVDX8G");
+ target.set_isa_version((fingerprint & 0x00ff000000000000) >> 48);
+ target.set_feature_code(fingerprint & 0x0000ffffffffffff);
+
+ constexpr std::array<uint64_t, 3> PP_MAP{8, 8, 8};
+ constexpr std::array<uint64_t, 3> ICP_MAP{16, 16, 16};
+ constexpr std::array<uint64_t, 3> OCP_MAP{16, 32, 64};
+ std::array<std::string, 3> ALU_MAP{"NONE", "ALL", "3D"};
+ constexpr std::array<uint64_t, 7> IMG_RD_MAP{13, 13, 12, 13, 12, 14, 14};
+ constexpr std::array<uint64_t, 7> WGT_RD_MAP{14, 13, 13, 12, 12, 14, 13};
+ constexpr std::array<uint64_t, 7> BIAS_RD_MAP{11, 11, 11, 11, 11, 11, 11};
+
+ auto ARCH = fingerprint & 0xf;
+ auto PP = PP_MAP[ARCH];
+ auto ICP = ICP_MAP[ARCH];
+ auto OCP = OCP_MAP[ARCH];
+ auto WGT_BANK_NUM = 16;
+
+ auto BATCH = (fingerprint & 0xf0) >> 4;
+ auto ALU = (fingerprint & 0xf00) >> 8;
+ auto ALU_MODE = ALU_MAP[ALU];
+ auto ALU_PP = (fingerprint & 0xf000) >> 12;
+ auto EL_PP = (fingerprint & 0xf0000) >> 16;
+ auto IMG_BG = (fingerprint & 0x3000000) >> 24;
+ auto LD_AUGM = (fingerprint & 0x4000000) >> 26;
+ // auto LD_MEAN = (fingerprint & 0x8000000) >> 27;
+ auto CV_LKRL = (fingerprint & 0x10000000) >> 28;
+ auto CV_RL6 = (fingerprint & 0x20000000) >> 29;
+ auto RDEPTH = (fingerprint & 0xf00000000) >> 32;
+ auto IMG_RD = IMG_RD_MAP[RDEPTH];
+ auto WGT_RD = WGT_RD_MAP[RDEPTH];
+ auto BIAS_RD = BIAS_RD_MAP[RDEPTH];
+ auto EL_MULT = (fingerprint & 0x1000000000) >> 36;
+ auto ISA = (fingerprint & 0x00ff000000000000) >> 48;
+
+ std::string NAME = "DPUCVDX8G_ISAx_CxBx_x";
+ char finger_hex[17];
+ sprintf(finger_hex, "%016" PRIX64, fingerprint);
+ NAME.replace(20, 1, finger_hex);
+ NAME.replace(18, 1, std::to_string(BATCH));
+ NAME.replace(16, 1, std::to_string(OCP));
+ NAME.replace(13, 1, std::to_string(ISA));
+ target.set_name(NAME);
+
+ auto base_id = 0U;
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ auto img_bank_group = target.add_bank_group();
+ img_bank_group->set_name("VB" + std::to_string(idx));
+ img_bank_group->set_type("Virtual");
+ img_bank_group->set_base_id(base_id);
+ img_bank_group->set_bank_num(PP);
+ img_bank_group->set_bank_width(ICP);
+ img_bank_group->set_bank_depth(1 << IMG_RD);
+ base_id += PP;
+ }
+ auto convw_bank_group = target.add_bank_group();
+ convw_bank_group->set_name("CONVW");
+ convw_bank_group->set_type("Param");
+ convw_bank_group->set_base_id(base_id);
+ convw_bank_group->set_bank_num(WGT_BANK_NUM);
+ convw_bank_group->set_bank_width(ICP);
+ convw_bank_group->set_bank_depth(1 << WGT_RD);
+ base_id += WGT_BANK_NUM;
+ if (ALU_MODE == "ALL" || ALU_MODE == "3D") {
+ auto dwconvw_bank_group = target.add_bank_group();
+ dwconvw_bank_group->set_name("DWCONVW");
+ dwconvw_bank_group->set_type("Param");
+ dwconvw_bank_group->set_base_id(base_id);
+ dwconvw_bank_group->set_bank_num(1);
+ dwconvw_bank_group->set_bank_width(ICP);
+ dwconvw_bank_group->set_bank_depth(1 << WGT_RD);
+ base_id += 1;
+ }
+ auto bias_bank_group = target.add_bank_group();
+ bias_bank_group->set_name("BIAS");
+ bias_bank_group->set_type("Param");
+ bias_bank_group->set_base_id(base_id);
+ bias_bank_group->set_bank_num(1);
+ bias_bank_group->set_bank_width(WGT_BANK_NUM);
+ bias_bank_group->set_bank_depth(1 << BIAS_RD);
+ base_id += 1;
+ if (ALU_MODE == "ALL" || ALU_MODE == "3D") {
+ auto dwbias_bank_group = target.add_bank_group();
+ dwbias_bank_group->set_name("DWCVBIAS");
+ dwbias_bank_group->set_type("Param");
+ dwbias_bank_group->set_base_id(base_id);
+ dwbias_bank_group->set_bank_num(1);
+ dwbias_bank_group->set_bank_width(ICP);
+ dwbias_bank_group->set_bank_depth(1 << BIAS_RD);
+ base_id += 1;
+ }
+
+ auto load_engine = target.mutable_load_engine();
+ load_engine->set_channel_parallel(ICP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ load_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+
+ auto save_engine = target.mutable_save_engine();
+ save_engine->set_channel_parallel(ICP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ save_engine->add_input_bank("VB" + std::to_string(idx));
+ }
+
+ auto conv_engine = target.mutable_conv_engine();
+ conv_engine->set_input_channel_parallel(ICP);
+ conv_engine->set_output_channel_parallel(OCP);
+ conv_engine->set_pixel_parallel(PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ conv_engine->add_input_bank("VB" + std::to_string(idx));
+ conv_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ conv_engine->set_weight_bank("CONVW");
+ conv_engine->set_bias_bank("BIAS");
+ if (LD_AUGM) {
+ conv_engine->mutable_channel_augmentation()->set_channel_num(ICP * 2);
+ }
+ auto conv_nonlinear = conv_engine->mutable_nonlinear();
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ if (CV_LKRL) {
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::leaky_relu);
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::hsigmoid);
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::hswish);
+ }
+ if (CV_RL6) {
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu_six);
+ }
+ auto conv_limit = conv_engine->mutable_conv_limit();
+ conv_limit->set_kernel_size("1-16");
+ conv_limit->set_stride("1-8");
+
+ auto eltwise_engine = target.mutable_eltwise_engine();
+ eltwise_engine->set_channel_parallel(ICP);
+ eltwise_engine->set_pixel_parallel(EL_PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ eltwise_engine->add_input_bank("VB" + std::to_string(idx));
+ eltwise_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ auto eltwise_nonlinear = eltwise_engine->mutable_nonlinear();
+ eltwise_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ eltwise_engine->add_elew_type(Target::Eltwise::add);
+ if (EL_MULT) {
+ eltwise_engine->add_elew_type(Target::Eltwise::mult);
+ }
+
+ auto alu_engine = target.mutable_alu_engine();
+ alu_engine->set_channel_parallel(ICP);
+ alu_engine->set_pixel_parallel(ALU_PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ alu_engine->add_input_bank("VB" + std::to_string(idx));
+ alu_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ if (ALU_MODE == "ALL" || ALU_MODE == "3D") {
+ alu_engine->set_weight_bank("DWCONVW");
+ alu_engine->set_bias_bank("DWCVBIAS");
+ }
+ auto alu_nonlinear = alu_engine->mutable_nonlinear();
+ alu_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ if (ALU_MODE == "ALL" || ALU_MODE == "3D") {
+ alu_nonlinear->add_nonlinear_type(Target::Nonlinear::relu_six);
+ }
+ if (ALU_MODE == "ALL" || ALU_MODE == "3D") {
+ alu_engine->add_alu_type(Target::Alu::dwconv);
+ alu_engine->add_alu_type(Target::Alu::prelu);
+ alu_engine->add_alu_type(Target::Alu::avg_pool);
+ alu_engine->add_alu_type(Target::Alu::max_pool);
+ alu_engine->add_alu_type(Target::Alu::leaky_relu);
+ alu_engine->add_alu_type(Target::Alu::max_reduce);
+ alu_engine->add_alu_type(Target::Alu::dwconv_no_bias);
+ alu_engine->add_alu_type(Target::Alu::hsigmoid);
+ }
+ if (ALU_MODE == "3D") {
+ alu_engine->add_alu_type(Target::Alu::w16b0);
+ }
+ auto alu_limit = alu_engine->mutable_alu_limit();
+ alu_limit->set_kernel_size("1-256");
+ if (ALU_MODE == "ALL") {
+ alu_limit->set_stride("1-8");
+ } else if (ALU_MODE == "3D") {
+ alu_limit->set_stride("1-256");
+ }
+ auto pad_limit = alu_engine->mutable_pad_limit();
+ pad_limit->set_pad_left("0-15");
+ pad_limit->set_pad_top("0-15");
+ pad_limit->set_pad_right("0-255");
+ pad_limit->set_pad_bottom("0-255");
+
+ target.set_batch(BATCH);
+
+ return target;
+}
+
+} // namespace ai
+} // namespace vitis
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include <inttypes.h>
+#include <array>
+#include <math.h>
+#include "vitis/ai/target_factory.hpp"
+#include <UniLog/UniLog.hpp>
+#include <iomanip>
+#include <iostream>
+
+namespace vitis {
+namespace ai {
+
+const Target create_target_DPUCVDX8G_ISA3(const std::uint64_t fingerprint) {
+ Target target;
+ target.set_type("DPUCVDX8G");
+ target.set_isa_version((fingerprint & 0x00ff000000000000) >> 48);
+ target.set_feature_code(fingerprint & 0x0000ffffffffffff);
+
+ constexpr std::array<uint64_t, 3> PP_MAP{8, 8, 8};
+ constexpr std::array<uint64_t, 3> ICP_MAP{16, 16, 16};
+ constexpr std::array<uint64_t, 3> OCP_MAP{16, 32, 64};
+ constexpr std::array<uint64_t, 7> IMG_RD_MAP{13, 13, 12, 13, 12, 14, 14};
+ constexpr std::array<uint64_t, 7> WGT_RD_MAP{14, 13, 13, 12, 12, 14, 13};
+ constexpr std::array<uint64_t, 7> BIAS_RD_MAP{11, 11, 11, 11, 11, 11, 11};
+
+ auto ARCH = fingerprint & 0xf;
+ auto PP = PP_MAP[ARCH];
+ auto ICP = ICP_MAP[ARCH];
+ auto OCP = OCP_MAP[ARCH];
+ auto WGT_BANK_NUM = 16;
+
+ auto BATCH = (fingerprint & 0xf0) >> 4;
+ auto ALU_PP = (fingerprint & 0xf00) >> 8;
+ auto RDEPTH = (fingerprint & 0xf000) >> 12;
+ auto IMG_RD = IMG_RD_MAP[RDEPTH];
+ auto WGT_RD = WGT_RD_MAP[RDEPTH];
+ auto BIAS_RD = BIAS_RD_MAP[RDEPTH];
+ auto IMG_BG = (fingerprint & 0x3000000) >> 24;
+ auto LD_AUGM = (fingerprint & 0x4000000) >> 26;
+ // auto LD_MEAN = (fingerprint & 0x8000000) >> 27;
+ auto CV_LKRL = (fingerprint & 0x10000000) >> 28;
+ auto DW_LKRL = (fingerprint & 0x20000000) >> 29;
+ // auto CV_WP = (uint64_t)pow(2,(fingerprint & 0x300000000) >> 32);
+ auto ALU_WP = (uint64_t)pow(2,(fingerprint & 0xc00000000) >> 34);
+ auto ISA = (fingerprint & 0x00ff000000000000) >> 48;
+
+ std::string NAME = "DPUCVDX8G_ISAx_CxBx_x";
+ char finger_hex[17];
+ sprintf(finger_hex, "%016" PRIX64, fingerprint);
+ NAME.replace(20, 1, finger_hex);
+ NAME.replace(18, 1, std::to_string(BATCH));
+ NAME.replace(16, 1, std::to_string(OCP));
+ NAME.replace(13, 1, std::to_string(ISA));
+ target.set_name(NAME);
+
+ if(ARCH >= PP_MAP.size()) {
+ UNI_LOG_FATAL(TARGET_FACTORY_INVALID_ARCH)
+ << "Unregistered fingerprint=0x" << std::hex
+ << std::setfill('0') << std::setw(16) << fingerprint
+ << " with invalid ARCH=0x" << std::hex << ARCH
+ << ", please check the HW configuration, or contact us.";
+ }
+
+ auto base_id = 0U;
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ auto img_bank_group = target.add_bank_group();
+ img_bank_group->set_name("VB" + std::to_string(idx));
+ img_bank_group->set_type("Virtual");
+ img_bank_group->set_base_id(base_id);
+ img_bank_group->set_bank_num(PP);
+ img_bank_group->set_bank_width(ICP);
+ img_bank_group->set_bank_depth(1 << IMG_RD);
+ base_id += PP;
+ }
+ auto convw_bank_group = target.add_bank_group();
+ convw_bank_group->set_name("CONVW");
+ convw_bank_group->set_type("Param");
+ convw_bank_group->set_base_id(base_id);
+ convw_bank_group->set_bank_num(WGT_BANK_NUM);
+ convw_bank_group->set_bank_width(ICP);
+ convw_bank_group->set_bank_depth(1 << WGT_RD);
+ base_id += WGT_BANK_NUM;
+ auto dwconvw_bank_group = target.add_bank_group();
+ dwconvw_bank_group->set_name("DWCONVW");
+ dwconvw_bank_group->set_type("Param");
+ dwconvw_bank_group->set_base_id(base_id);
+ dwconvw_bank_group->set_bank_num(1);
+ dwconvw_bank_group->set_bank_width(ICP);
+ dwconvw_bank_group->set_bank_depth(1 << WGT_RD);
+ base_id += 1;
+ auto bias_bank_group = target.add_bank_group();
+ bias_bank_group->set_name("BIAS");
+ bias_bank_group->set_type("Param");
+ bias_bank_group->set_base_id(base_id);
+ bias_bank_group->set_bank_num(1);
+ bias_bank_group->set_bank_width(WGT_BANK_NUM);
+ bias_bank_group->set_bank_depth(1 << BIAS_RD);
+ base_id += 1;
+ auto dwbias_bank_group = target.add_bank_group();
+ dwbias_bank_group->set_name("DWCVBIAS");
+ dwbias_bank_group->set_type("Param");
+ dwbias_bank_group->set_base_id(base_id);
+ dwbias_bank_group->set_bank_num(1);
+ dwbias_bank_group->set_bank_width(ICP);
+ dwbias_bank_group->set_bank_depth(1 << BIAS_RD);
+ base_id += 1;
+
+ auto load_engine = target.mutable_load_engine();
+ load_engine->set_channel_parallel(ICP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ load_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+
+ auto save_engine = target.mutable_save_engine();
+ save_engine->set_channel_parallel(ICP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ save_engine->add_input_bank("VB" + std::to_string(idx));
+ }
+
+ auto conv_engine = target.mutable_conv_engine();
+ conv_engine->set_input_channel_parallel(ICP);
+ conv_engine->set_output_channel_parallel(OCP);
+ conv_engine->set_pixel_parallel(PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ conv_engine->add_input_bank("VB" + std::to_string(idx));
+ conv_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ conv_engine->set_weight_bank("CONVW");
+ conv_engine->set_bias_bank("BIAS");
+ if (LD_AUGM) {
+ conv_engine->mutable_channel_augmentation()->set_channel_num(ICP * 2);
+ }
+ auto conv_nonlinear = conv_engine->mutable_nonlinear();
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ if (CV_LKRL) {
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::leaky_relu);
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::hsigmoid);
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::hswish);
+ }
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu_six);
+ auto conv_limit = conv_engine->mutable_conv_limit();
+ conv_limit->set_kernel_size("1-16");
+ conv_limit->set_stride("1-8");
+ conv_limit->set_stride_out_h("1-8");
+
+ auto eltwise_engine = target.mutable_eltwise_engine();
+ eltwise_engine->set_channel_parallel(ICP);
+ eltwise_engine->set_pixel_parallel(ALU_PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ eltwise_engine->add_input_bank("VB" + std::to_string(idx));
+ eltwise_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ auto eltwise_nonlinear = eltwise_engine->mutable_nonlinear();
+ eltwise_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ eltwise_engine->add_elew_type(Target::Eltwise::add);
+ eltwise_engine->add_elew_type(Target::Eltwise::mult);
+
+ auto alu_engine = target.mutable_alu_engine();
+ alu_engine->set_channel_parallel(ICP);
+ alu_engine->set_pixel_parallel(ALU_PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ alu_engine->add_input_bank("VB" + std::to_string(idx));
+ alu_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ alu_engine->set_weight_bank("DWCONVW");
+ alu_engine->set_bias_bank("DWCVBIAS");
+ auto alu_nonlinear = alu_engine->mutable_nonlinear();
+ alu_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ if (DW_LKRL) {
+ alu_nonlinear->add_nonlinear_type(Target::Nonlinear::leaky_relu);
+ }
+ alu_nonlinear->add_nonlinear_type(Target::Nonlinear::relu_six);
+ alu_engine->add_alu_type(Target::Alu::dwconv);
+ alu_engine->add_alu_type(Target::Alu::prelu);
+ alu_engine->add_alu_type(Target::Alu::avg_pool);
+ alu_engine->add_alu_type(Target::Alu::max_pool);
+ alu_engine->add_alu_type(Target::Alu::leaky_relu);
+ alu_engine->add_alu_type(Target::Alu::max_reduce);
+ alu_engine->add_alu_type(Target::Alu::dwconv_no_bias);
+ alu_engine->add_alu_type(Target::Alu::hsigmoid);
+ alu_engine->add_alu_type(Target::Alu::w16b0);
+ auto alu_limit = alu_engine->mutable_alu_limit();
+ alu_limit->set_kernel_size("1-256");
+ alu_limit->set_stride("1-256");
+ alu_limit->set_stride_out_h("1-" + std::to_string((ALU_WP==1||PP/ALU_WP>=4)?(4):(PP/ALU_WP)));
+ auto pad_limit = alu_engine->mutable_pad_limit();
+ pad_limit->set_pad_left("0-15");
+ pad_limit->set_pad_top("0-15");
+ pad_limit->set_pad_right("0-255");
+ pad_limit->set_pad_bottom("0-255");
+
+ target.set_batch(BATCH);
+
+ return target;
+}
+
+} // namespace ai
+} // namespace vitis
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include <inttypes.h>
+#include <array>
+#include <math.h>
+#include "vitis/ai/target_factory.hpp"
+#include <UniLog/UniLog.hpp>
+#include <iomanip>
+#include <iostream>
+
+namespace vitis {
+namespace ai {
+
+const Target create_target_DPUCZDX8G_ISA1(const std::uint64_t fingerprint) {
+ Target target;
+ target.set_type("DPUCZDX8G");
+ target.set_isa_version((fingerprint & 0x00ff000000000000) >> 48);
+ target.set_feature_code(fingerprint & 0x0000ffffffffffff);
+
+ constexpr std::array<uint64_t, 12> PP_MAP{ 4, 4, 8, 4, 8, 8,
+ 8, 8, 4, 2, 2, 2};
+ constexpr std::array<uint64_t, 12> ICP_MAP{8, 10, 8, 12, 10, 12,
+ 14, 16, 4, 6, 8, 4};
+ constexpr std::array<uint64_t, 12> OCP_MAP{8, 10, 8, 12, 10, 12,
+ 14, 16, 4, 6, 8, 4};
+
+ auto ARCH = fingerprint & 0xf;
+ auto PP = PP_MAP[ARCH];
+ auto ICP = ICP_MAP[ARCH];
+ auto OCP = OCP_MAP[ARCH];
+ auto PEAK = PP * ICP * OCP * 2;
+
+ auto ALU_PP = (fingerprint & 0xf00) >> 8;
+ auto IMG_BG = (fingerprint & 0x3000000) >> 24;
+ auto LD_AUGM = (fingerprint & 0x4000000) >> 26;
+ // auto LD_MEAN = (fingerprint & 0x8000000) >> 27;
+ auto CV_LKRL = (fingerprint & 0x10000000) >> 28;
+ auto DW_LKRL = (fingerprint & 0x20000000) >> 29;
+ auto CV_WP = (uint64_t)pow(2,(fingerprint & 0x300000000) >> 32);
+ auto ALU_WP = (uint64_t)pow(2,(fingerprint & 0xc00000000) >> 34);
+ auto ISA = (fingerprint & 0x00ff000000000000) >> 48;
+
+ std::string NAME = "DPUCZDX8G_ISAx_Bx_x";
+ char finger_hex[17];
+ sprintf(finger_hex, "%016" PRIX64, fingerprint);
+ NAME.replace(18, 1, finger_hex);
+ NAME.replace(16, 1, std::to_string(PEAK));
+ NAME.replace(13, 1, std::to_string(ISA));
+ target.set_name(NAME);
+
+ if(ARCH >= PP_MAP.size()) {
+ UNI_LOG_FATAL(TARGET_FACTORY_INVALID_ARCH)
+ << "Unregistered fingerprint=0x" << std::hex
+ << std::setfill('0') << std::setw(16) << fingerprint
+ << " with invalid ARCH=0x" << std::hex << ARCH
+ << ", please check the HW configuration, or contact us.";
+ }
+
+ auto base_id = 0U;
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ auto img_bank_group = target.add_bank_group();
+ img_bank_group->set_name("VB" + std::to_string(idx));
+ img_bank_group->set_type("Virtual");
+ img_bank_group->set_base_id(base_id);
+ img_bank_group->set_bank_num(PP);
+ img_bank_group->set_bank_width(ICP);
+ img_bank_group->set_bank_depth(2048);
+ base_id += PP;
+ }
+ auto convw_bank_group = target.add_bank_group();
+ convw_bank_group->set_name("CONVW");
+ convw_bank_group->set_type("Param");
+ convw_bank_group->set_base_id(base_id);
+ convw_bank_group->set_bank_num(OCP);
+ convw_bank_group->set_bank_width(ICP);
+ convw_bank_group->set_bank_depth(2048);
+ base_id += OCP;
+ auto dwconvw_bank_group = target.add_bank_group();
+ dwconvw_bank_group->set_name("DWCONVW");
+ dwconvw_bank_group->set_type("Param");
+ dwconvw_bank_group->set_base_id(base_id);
+ dwconvw_bank_group->set_bank_num(1);
+ dwconvw_bank_group->set_bank_width(ICP);
+ dwconvw_bank_group->set_bank_depth(2048);
+ base_id += 1;
+ auto bias_bank_group = target.add_bank_group();
+ bias_bank_group->set_name("BIAS");
+ bias_bank_group->set_type("Param");
+ bias_bank_group->set_base_id(base_id);
+ bias_bank_group->set_bank_num(1);
+ bias_bank_group->set_bank_width(ICP);
+ bias_bank_group->set_bank_depth(2048);
+ base_id += 1;
+
+ auto load_engine = target.mutable_load_engine();
+ load_engine->set_channel_parallel(ICP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ load_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+
+ auto save_engine = target.mutable_save_engine();
+ save_engine->set_channel_parallel(ICP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ save_engine->add_input_bank("VB" + std::to_string(idx));
+ }
+
+ auto conv_engine = target.mutable_conv_engine();
+ conv_engine->set_input_channel_parallel(ICP);
+ conv_engine->set_output_channel_parallel(OCP);
+ conv_engine->set_pixel_parallel(PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ conv_engine->add_input_bank("VB" + std::to_string(idx));
+ conv_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ conv_engine->set_weight_bank("CONVW");
+ conv_engine->set_bias_bank("BIAS");
+ if (LD_AUGM) {
+ conv_engine->mutable_channel_augmentation()->set_channel_num(ICP * 2);
+ }
+ auto conv_nonlinear = conv_engine->mutable_nonlinear();
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ if (CV_LKRL) {
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::leaky_relu);
+ }
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu_six);
+ auto conv_limit = conv_engine->mutable_conv_limit();
+ conv_limit->set_kernel_size("1-16");
+ conv_limit->set_stride("1-8");
+ conv_limit->set_stride_out_h("1-" + std::to_string((CV_WP==1||PP/CV_WP>=4)?(4):(PP/CV_WP)));
+
+ auto eltwise_engine = target.mutable_eltwise_engine();
+ eltwise_engine->set_channel_parallel(ICP);
+ eltwise_engine->set_pixel_parallel(ALU_PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ eltwise_engine->add_input_bank("VB" + std::to_string(idx));
+ eltwise_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ auto eltwise_nonlinear = eltwise_engine->mutable_nonlinear();
+ eltwise_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ eltwise_engine->add_elew_type(Target::Eltwise::add);
+ eltwise_engine->add_elew_type(Target::Eltwise::mult);
+
+ auto alu_engine = target.mutable_alu_engine();
+ alu_engine->set_channel_parallel(ICP);
+ alu_engine->set_pixel_parallel(ALU_PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ alu_engine->add_input_bank("VB" + std::to_string(idx));
+ alu_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ alu_engine->set_weight_bank("DWCONVW");
+ alu_engine->set_bias_bank("BIAS");
+ auto alu_nonlinear = alu_engine->mutable_nonlinear();
+ alu_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ if (DW_LKRL) {
+ alu_nonlinear->add_nonlinear_type(Target::Nonlinear::leaky_relu);
+ }
+ alu_nonlinear->add_nonlinear_type(Target::Nonlinear::relu_six);
+ alu_engine->add_alu_type(Target::Alu::dwconv);
+ alu_engine->add_alu_type(Target::Alu::prelu);
+ alu_engine->add_alu_type(Target::Alu::avg_pool);
+ alu_engine->add_alu_type(Target::Alu::max_pool);
+ alu_engine->add_alu_type(Target::Alu::leaky_relu);
+ alu_engine->add_alu_type(Target::Alu::max_reduce);
+ alu_engine->add_alu_type(Target::Alu::dwconv_no_bias);
+ alu_engine->add_alu_type(Target::Alu::hsigmoid);
+ alu_engine->add_alu_type(Target::Alu::w16b0);
+ auto alu_limit = alu_engine->mutable_alu_limit();
+ alu_limit->set_kernel_size("1-256");
+ alu_limit->set_stride("1-256");
+ alu_limit->set_stride_out_h("1-" + std::to_string((ALU_WP==1||PP/ALU_WP>=4)?(4):(PP/ALU_WP)));
+ auto pad_limit = alu_engine->mutable_pad_limit();
+ pad_limit->set_pad_left("0-15");
+ pad_limit->set_pad_top("0-15");
+ pad_limit->set_pad_right("0-255");
+ pad_limit->set_pad_bottom("0-255");
+
+ return target;
+}
+
+} // namespace ai
+} // namespace vitis
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+#include <inttypes.h>
+
+#include <array>
+
+#include "vitis/ai/target_factory.hpp"
+
+namespace vitis {
+namespace ai {
+
+const Target create_target_v2(const std::uint64_t fingerprint) {
+ Target target;
+ target.set_name("DPUCZDX8G_CUSTOMIZED");
+ target.set_type("DPUCZDX8G");
+ target.set_isa_version((fingerprint & 0x00ff000000000000) >> 48);
+ target.set_feature_code(fingerprint & 0x0000ffffffffffff);
+
+ constexpr std::array<uint64_t, 11> PP_MAP{4, 4, 8, 4, 8, 8, 8, 8, 4, 2, 2};
+ constexpr std::array<uint64_t, 11> ICP_MAP{8, 10, 8, 12, 10, 12,
+ 14, 16, 4, 6, 8};
+ constexpr std::array<uint64_t, 11> OCP_MAP{8, 10, 8, 12, 10, 12,
+ 14, 16, 4, 6, 8};
+
+ auto ARCH = fingerprint & 0xf;
+ auto PP = PP_MAP[ARCH];
+ auto ICP = ICP_MAP[ARCH];
+ auto OCP = OCP_MAP[ARCH];
+ auto PEAK = PP * ICP * OCP * 2;
+
+ auto PL_PP = (fingerprint & 0xf00) >> 8;
+ auto DW_PP = (fingerprint & 0xf000) >> 12;
+ auto EL_PP = (fingerprint & 0xf0000) >> 16;
+ auto IMG_BG = (fingerprint & 0x3000000) >> 24;
+ auto LD_AUGM = (fingerprint & 0x4000000) >> 26;
+ // auto LD_MEAN = (fingerprint & 0x8000000) >> 27;
+ auto CV_LKRL = (fingerprint & 0x10000000) >> 28;
+ auto CV_RL6 = (fingerprint & 0x20000000) >> 29;
+ auto PL_AVG = (fingerprint & 0x40000000) >> 30;
+ auto DW_RL6 = (fingerprint & 0x80000000) >> 31;
+ auto EL_MULT = (fingerprint & 0x1000000000) >> 36;
+ auto PL_DSM = (fingerprint & 0x2000000000) >> 37;
+ auto ISA = (fingerprint & 0x00ff000000000000) >> 48;
+
+ std::string NAME = "DPUCZDX8G_ISAx_Bx_x";
+ char finger_hex[17];
+ sprintf(finger_hex, "%016" PRIX64, fingerprint);
+ NAME.replace(18, 1, finger_hex);
+ NAME.replace(16, 1, std::to_string(PEAK));
+ NAME.replace(13, 1, std::to_string(ISA));
+ target.set_name(NAME);
+
+ auto base_id = 0U;
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ auto img_bank_group = target.add_bank_group();
+ img_bank_group->set_name("VB" + std::to_string(idx));
+ img_bank_group->set_type("Virtual");
+ img_bank_group->set_base_id(base_id);
+ img_bank_group->set_bank_num(PP);
+ img_bank_group->set_bank_width(ICP);
+ img_bank_group->set_bank_depth(2048);
+ base_id += PP;
+ }
+ auto convw_bank_group = target.add_bank_group();
+ convw_bank_group->set_name("CONVW");
+ convw_bank_group->set_type("Param");
+ convw_bank_group->set_base_id(base_id);
+ convw_bank_group->set_bank_num(OCP);
+ convw_bank_group->set_bank_width(ICP);
+ convw_bank_group->set_bank_depth(2048);
+ base_id += OCP;
+ if (DW_PP) {
+ auto dwconvw_bank_group = target.add_bank_group();
+ dwconvw_bank_group->set_name("DWCONVW");
+ dwconvw_bank_group->set_type("Param");
+ dwconvw_bank_group->set_base_id(base_id);
+ dwconvw_bank_group->set_bank_num(1);
+ dwconvw_bank_group->set_bank_width(ICP);
+ dwconvw_bank_group->set_bank_depth(2048);
+ base_id += 1;
+ }
+ auto bias_bank_group = target.add_bank_group();
+ bias_bank_group->set_name("BIAS");
+ bias_bank_group->set_type("Param");
+ bias_bank_group->set_base_id(base_id);
+ bias_bank_group->set_bank_num(1);
+ bias_bank_group->set_bank_width(ICP);
+ bias_bank_group->set_bank_depth(2048);
+ base_id += 1;
+
+ auto load_engine = target.mutable_load_engine();
+ load_engine->set_channel_parallel(ICP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ load_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+
+ auto save_engine = target.mutable_save_engine();
+ save_engine->set_channel_parallel(ICP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ save_engine->add_input_bank("VB" + std::to_string(idx));
+ }
+
+ auto conv_engine = target.mutable_conv_engine();
+ conv_engine->set_input_channel_parallel(ICP);
+ conv_engine->set_output_channel_parallel(OCP);
+ conv_engine->set_pixel_parallel(PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ conv_engine->add_input_bank("VB" + std::to_string(idx));
+ conv_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ conv_engine->set_weight_bank("CONVW");
+ conv_engine->set_bias_bank("BIAS");
+ if (LD_AUGM) {
+ conv_engine->mutable_channel_augmentation()->set_channel_num(ICP * 2);
+ }
+ auto conv_nonlinear = conv_engine->mutable_nonlinear();
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ if (CV_LKRL) {
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::leaky_relu);
+ }
+ if (CV_RL6) {
+ conv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu_six);
+ }
+ auto conv_limit = conv_engine->mutable_conv_limit();
+ conv_limit->set_kernel_size("1-16");
+ conv_limit->set_stride("1-8");
+
+ auto eltwise_engine = target.mutable_eltwise_engine();
+ eltwise_engine->set_channel_parallel(ICP);
+ eltwise_engine->set_pixel_parallel(EL_PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ eltwise_engine->add_input_bank("VB" + std::to_string(idx));
+ eltwise_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ auto eltwise_nonlinear = eltwise_engine->mutable_nonlinear();
+ eltwise_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ eltwise_engine->add_elew_type(Target::Eltwise::add);
+ if (EL_MULT) {
+ eltwise_engine->add_elew_type(Target::Eltwise::mult);
+ }
+
+ auto pool_engine = target.mutable_pool_engine();
+ pool_engine->set_channel_parallel(ICP);
+ pool_engine->set_pixel_parallel(PL_PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ pool_engine->add_input_bank("VB" + std::to_string(idx));
+ pool_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ auto pool_nonlinear = pool_engine->mutable_nonlinear();
+ pool_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ pool_engine->add_pool_type(Target::Pool::max);
+ auto max_limit = pool_engine->mutable_max_limit();
+ max_limit->set_kernel_size("1-8");
+ max_limit->set_stride("1-8");
+ if (PL_AVG) {
+ pool_engine->add_pool_type(Target::Pool::avg);
+ auto avg_limit = pool_engine->mutable_avg_limit();
+ avg_limit->set_kernel_size("2-8");
+ avg_limit->set_stride("1-8");
+ }
+ if (PL_DSM) {
+ pool_engine->add_pool_type(Target::Pool::max_reduce);
+ }
+
+ if (DW_PP) {
+ auto dwconv_engine = target.mutable_dwconv_engine();
+ dwconv_engine->set_channel_parallel(ICP);
+ dwconv_engine->set_pixel_parallel(DW_PP);
+ for (auto idx = 0U; idx < IMG_BG; idx++) {
+ dwconv_engine->add_input_bank("VB" + std::to_string(idx));
+ dwconv_engine->add_output_bank("VB" + std::to_string(idx));
+ }
+ dwconv_engine->set_weight_bank("DWCONVW");
+ dwconv_engine->set_bias_bank("BIAS");
+ auto dwconv_nonlinear = dwconv_engine->mutable_nonlinear();
+ dwconv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu);
+ if (DW_RL6) {
+ dwconv_nonlinear->add_nonlinear_type(Target::Nonlinear::relu_six);
+ }
+ auto dwconv_limit = dwconv_engine->mutable_dwconv_limit();
+ dwconv_limit->set_kernel_size("1-16");
+ dwconv_limit->set_stride("1-8");
+ }
+
+ return target;
+}
+
+} // namespace ai
+} // namespace vitis
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "UniLog/ErrorCode.hpp"
+
+REGISTER_ERROR_CODE(TARGET_FACTORY_MULTI_REGISTERED_TARGET,
+ "Multiple registration of target!", "");
+REGISTER_ERROR_CODE(TARGET_FACTORY_UNREGISTERED_TARGET, "Unregistered target!",
+ "");
+
+REGISTER_ERROR_CODE(TARGET_FACTORY_INVALID_TYPE, "Invalid target type!", "");
+REGISTER_ERROR_CODE(TARGET_FACTORY_INVALID_ISA_VERSION,
+ "Invalid target ISA version!", "");
+REGISTER_ERROR_CODE(TARGET_FACTORY_INVALID_FEATURE_CODE,
+ "Invalid target feature code!", "");
+REGISTER_ERROR_CODE(TARGET_FACTORY_INVALID_ARCH,
+ "Invalid target arch!", "");
+
+REGISTER_ERROR_CODE(TARGET_FACTORY_PARSE_TARGET_FAIL,
+ "Fail to parse target from prototxt!", "");
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License. You may obtain a copy of
+# the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations under
+# the License.
+
+vai_add_pybind11_module(wrapper MODULE_NAME target_factory wrapper.cpp)
+target_link_libraries(wrapper PRIVATE ${PROJECT_NAME} unilog::unilog)
--- /dev/null
+/**
+ * Copyright 2019 Xilinx Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// python 3.7 deprecate PyCreateThread, but pybind11 2.2.3 still uses
+// this function.
+#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
+#include <pybind11/pybind11.h>
+#include "vitis/ai/target_factory.hpp"
+
+namespace py = pybind11;
+
+namespace vitis {
+namespace ai {
+
+PYBIND11_MODULE(target_factory, m) {
+ py::class_<Target>(m, "Target");
+ m.def("get_target_by_name",
+ [](const std::string& name) { return target_factory()->create(name); });
+ m.def("get_target_by_fingerprint", [](const std::uint64_t fingerprint) {
+ return target_factory()->create(fingerprint);
+ });
+ m.def("dump_proto_txt", [](const Target& target, const std::string& file) {
+ return target_factory()->dump(target, file);
+ });
+ m.def("is_registered_target", [](const std::string& name) {
+ return target_factory()->is_registered_target(name);
+ });
+}
+} // namespace ai
+} // namespace vitis
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+syntax = "proto3";
+
+package vitis.ai;
+
+message Target {
+ message BankGroup {
+ string name = 1;
+ string type = 9;
+ uint32 base_id = 2;
+ uint32 bank_num = 3;
+ uint32 bank_width = 4;
+ uint32 bank_depth = 5;
+ uint32 word_width = 6;
+ bool cyclic = 7;
+ message AdjustableWordWidth {
+ uint32 scale = 1;
+ enum WordWidthSwitch {
+ DataBit_x_BankDepth = 0;
+ DataBit_x_BankWidth = 1;
+ }
+ WordWidthSwitch word_width_switch = 2;
+ }
+ AdjustableWordWidth adjustable_word_width = 8;
+ }
+
+ message Load {
+ message MeanvalueReduction { string meanvalue_bank = 1; }
+ message FixIFMPortWidth { uint32 port_width = 1; }
+ message WeightSplit { bool wgt_split = 1; }
+ message LoadMode {
+ enum SrcType {
+ ddr = 0;
+ imm = 1;
+ }
+ repeated SrcType src_type = 1;
+ }
+ uint32 channel_parallel = 1;
+ repeated string output_bank = 2;
+ MeanvalueReduction meanvalue_reduction = 3;
+ FixIFMPortWidth fix_ifm_port_width = 4;
+ WeightSplit weight_split = 5;
+ LoadMode load_mode = 6;
+ }
+
+ message Save {
+ message FixIFMPortWidth { uint32 port_width = 1; }
+ uint32 channel_parallel = 1;
+ repeated string input_bank = 2;
+ FixIFMPortWidth fix_ifm_port_width = 3;
+ }
+
+ message Nonlinear {
+ enum NonlinearType {
+ relu = 0;
+ prelu = 1;
+ leaky_relu = 2;
+ relu_six = 3;
+ hsigmoid = 4;
+ hswish = 5;
+ }
+ repeated NonlinearType nonlinear_type = 1;
+ }
+
+ message PadLimit {
+ string pad_left = 1;
+ string pad_right = 2;
+ string pad_top = 3;
+ string pad_bottom = 4;
+ }
+
+ message Conv {
+ uint32 input_channel_parallel = 1;
+ uint32 output_channel_parallel = 2;
+ uint32 pixel_parallel = 3;
+ repeated string input_bank = 4;
+ repeated string output_bank = 10;
+ message OutputBankGroup { repeated string output_bank = 1; }
+ repeated OutputBankGroup output_bank_group = 5;
+ string weight_bank = 6;
+ string bias_bank = 7;
+ message ChannelAugmentation { uint32 channel_num = 1; }
+ ChannelAugmentation channel_augmentation = 8;
+ Nonlinear nonlinear = 9;
+ message ConvLimit {
+ string kernel_size = 1;
+ string stride = 2;
+ string stride_out_h = 3;
+ }
+ ConvLimit conv_limit = 11;
+ }
+
+ message Eltwise {
+ uint32 channel_parallel = 1;
+ uint32 pixel_parallel = 2;
+ repeated string input_bank = 3;
+ repeated string output_bank = 4;
+ Nonlinear nonlinear = 5;
+ enum ElewType {
+ add = 0;
+ mult = 1;
+ }
+ repeated ElewType elew_type = 6;
+ message ConvCascade {
+ uint32 pixel_parallel = 1;
+ }
+ ConvCascade conv_cascade = 7;
+ }
+
+ message Pool {
+ uint32 channel_parallel = 1;
+ uint32 pixel_parallel = 2;
+ repeated string input_bank = 3;
+ repeated string output_bank = 4;
+ enum PoolType {
+ max = 0;
+ avg = 1;
+ max_reduce = 2;
+ }
+ repeated PoolType pool_type = 5;
+ Nonlinear nonlinear = 6;
+ message AvgLimit {
+ string kernel_size = 1;
+ string stride = 2;
+ }
+ AvgLimit avg_limit = 7;
+ message MaxLimit {
+ string kernel_size = 1;
+ string stride = 2;
+ }
+ MaxLimit max_limit = 8;
+ }
+
+ message Dwconv {
+ uint32 channel_parallel = 1;
+ uint32 pixel_parallel = 2;
+ repeated string input_bank = 3;
+ repeated string output_bank = 4;
+ string weight_bank = 5;
+ string bias_bank = 6;
+ Nonlinear nonlinear = 7;
+ message DwconvLimit {
+ string kernel_size = 1;
+ string stride = 2;
+ }
+ DwconvLimit dwconv_limit = 8;
+ }
+
+ message Move {
+ uint32 input_channel_parallel = 1;
+ uint32 output_channel_parallel = 2;
+ uint32 pixel_parallel = 3;
+ repeated string input_bank = 4;
+ repeated string output_bank = 5;
+ }
+
+ message Threshold {
+ uint32 channel_parallel = 1;
+ uint32 pixel_parallel = 2;
+ repeated string input_bank = 3;
+ repeated string output_bank = 4;
+ string param_bank = 5;
+ }
+
+ message Alu {
+ uint32 channel_parallel = 1;
+ uint32 pixel_parallel = 2;
+ repeated string input_bank = 3;
+ repeated string output_bank = 4;
+ string weight_bank = 5;
+ string bias_bank = 6;
+ enum AluType {
+ dwconv = 0;
+ prelu = 1;
+ avg_pool = 2;
+ max_pool = 3;
+ leaky_relu = 4;
+ max_reduce = 5;
+ dwconv_no_bias = 6;
+ hsigmoid = 7;
+ w16b0 = 8;
+ }
+ repeated AluType alu_type = 7;
+ Nonlinear nonlinear = 8;
+ message AluLimit {
+ string kernel_size = 1;
+ string stride = 2;
+ string stride_out_h = 3;
+ }
+ AluLimit alu_limit = 9;
+ PadLimit pad_limit = 10;
+ }
+
+ string name = 1;
+ string type = 2;
+ uint64 isa_version = 3;
+ uint64 feature_code = 4;
+
+ repeated BankGroup bank_group = 5;
+
+ Load load_engine = 6;
+ Save save_engine = 7;
+ Conv conv_engine = 8;
+ Eltwise eltwise_engine = 9;
+ Pool pool_engine = 10;
+ Dwconv dwconv_engine = 11;
+ Move move_engine = 12;
+ Threshold threshold_engine = 13;
+ Alu alu_engine = 15;
+
+ uint32 batch = 14;
+}
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "vitis/ai/target_factory.hpp"
+
+#include <fcntl.h>
+#ifdef _WIN32
+ #include <io.h>
+#endif
+#include <google/protobuf/io/zero_copy_stream_impl.h>
+#include <google/protobuf/text_format.h>
+
+#include <UniLog/UniLog.hpp>
+#include <iomanip>
+#include <iostream>
+#include <map>
+#include <memory>
+#include <mutex>
+#include <sstream>
+#include <string>
+
+#include "config.hpp"
+#include "target_list.hpp"
+
+namespace vitis {
+namespace ai {
+
+static uint64_t type2int(const std::string& type) {
+ uint32_t ret = 0U;
+ if (type == "DPUCZDX8G")
+ ret = 1U;
+ else if (type == "DPUCAHX8H")
+ ret = 2U;
+ else if (type == "DPUCAHX8L")
+ ret = 3U;
+ else if (type == "DPUCZDI4G")
+ ret = 4U;
+ else if (type == "DPUCVDX8H")
+ ret = 5U;
+ else if (type == "DPUCVDX8G")
+ ret = 6U;
+ else if (type == "DPUCADF8H")
+ ret = 7U;
+ else
+ UNI_LOG_FATAL(TARGET_FACTORY_INVALID_TYPE) << type;
+ return ret;
+}
+
+static std::string int2type(uint64_t type) {
+ std::string ret = "";
+ if (type == 1U)
+ ret = "DPUCZDX8G";
+ else if (type == 2U)
+ ret = "DPUCAHX8H";
+ else if (type == 3U)
+ ret = "DPUCAHX8L";
+ else if (type == 4U)
+ ret = "DPUCZDI4G";
+ else if (type == 5U)
+ ret = "DPUCVDX8H";
+ else if (type == 6U)
+ ret = "DPUCVDX8G";
+ else if (type == 7U)
+ ret = "DPUCADF8H";
+ else
+ UNI_LOG_FATAL(TARGET_FACTORY_INVALID_TYPE) << type;
+ return ret;
+}
+
+std::string to_string(const std::map<std::string, std::uint64_t>& value) {
+ std::ostringstream str;
+ int c = 0;
+ str << "{";
+ for (auto& x : value) {
+ if (c++ != 0) {
+ str << ",";
+ }
+ str << x.first << "=>" << std::hex << "0x" << x.second << std::dec;
+ }
+ str << "}";
+ return str.str();
+};
+
+const Target create_target_v2(const std::uint64_t fingerprint);
+const Target create_target_DPUCZDX8G_ISA1(const std::uint64_t fingerprint);
+const Target create_target_DPUCVDX8G_ISA2(const std::uint64_t fingerprint);
+const Target create_target_DPUCVDX8G_ISA3(const std::uint64_t fingerprint);
+
+class TargetFactoryImp : public TargetFactory {
+ public:
+ const Target create(const std::string& name) const override {
+ return this->create(this->get_fingerprint(name));
+ }
+
+ const Target create(const std::string& type, std::uint64_t isa_version,
+ std::uint64_t feature_code) const override {
+ return this->create(this->get_fingerprint(type, isa_version, feature_code));
+ }
+
+ const Target create(const std::uint64_t fingerprint) const override {
+ if (map_fingerprint_target_.count(fingerprint) != 0) {
+ return map_fingerprint_target_.at(fingerprint);
+ } else {
+ auto type = int2type(fingerprint >> 56);
+ auto isa_version = ((fingerprint & 0x00ff000000000000) >> 48);
+ if (type == "DPUCZDX8G" && isa_version == 0) {
+ return create_target_v2(fingerprint);
+ } else if (type == "DPUCZDX8G" && isa_version == 1) {
+ return create_target_DPUCZDX8G_ISA1(fingerprint);
+ } else if (type == "DPUCVDX8G" && isa_version == 2) {
+ return create_target_DPUCVDX8G_ISA2(fingerprint);
+ } else if (type == "DPUCVDX8G" && isa_version == 3) {
+ return create_target_DPUCVDX8G_ISA3(fingerprint);
+ } else {
+ UNI_LOG_FATAL(TARGET_FACTORY_UNREGISTERED_TARGET)
+ << "Cannot find or create target with fingerprint=0x" << std::hex
+ << std::setfill('0') << std::setw(16) << fingerprint;
+ Target target;
+ return target;
+ }
+ }
+ }
+
+ const std::uint64_t get_fingerprint(const std::string& name) const override {
+ UNI_LOG_CHECK(map_name_fingerprint_.count(name) != 0,
+ TARGET_FACTORY_UNREGISTERED_TARGET)
+ << "Cannot find target with name " << name
+ << ", valid names are: " << to_string(map_name_fingerprint_);
+ return map_name_fingerprint_.at(name);
+ }
+
+ const std::uint64_t get_fingerprint(
+ const std::string& type, std::uint64_t isa_version,
+ std::uint64_t feature_code) const override {
+ uint64_t fingureprint = 0U;
+ UNI_LOG_CHECK((feature_code & 0xffff000000000000) == 0,
+ TARGET_FACTORY_INVALID_ISA_VERSION)
+ << "0x" << std::hex << std::setfill('0') << std::setw(16) << feature_code;
+ UNI_LOG_CHECK((isa_version & 0xffffffffffffff00) == 0,
+ TARGET_FACTORY_INVALID_FEATURE_CODE)
+ << "0x" << std::hex << std::setfill('0') << std::setw(16) << isa_version;
+ fingureprint |= feature_code;
+ fingureprint |= isa_version << 48;
+ fingureprint |= type2int(type) << 56;
+ return fingureprint;
+ }
+
+ void dump(const Target& target, const std::string& file) const override {
+ auto fd = open(file.c_str(), O_WRONLY | O_CREAT | O_TRUNC, 00644);
+ google::protobuf::io::FileOutputStream fstream(fd);
+ google::protobuf::TextFormat::Print(target, &fstream);
+ }
+
+
+ bool is_registered_target(const std::string& name) const override {
+ return map_name_fingerprint_.count(name) != 0;
+ }
+
+ public:
+ void register_h(const Target& target) {
+ auto name = target.name();
+ auto fingerprint = this->get_fingerprint(
+ target.type(), target.isa_version(), target.feature_code());
+ UNI_LOG_CHECK(map_fingerprint_target_.count(fingerprint) == 0,
+ TARGET_FACTORY_MULTI_REGISTERED_TARGET)
+ << "fingerprint=0x" << std::hex << std::setw(16) << std::setfill('0')
+ << fingerprint;
+ UNI_LOG_CHECK(map_name_fingerprint_.count(name) == 0,
+ TARGET_FACTORY_MULTI_REGISTERED_TARGET)
+ << "name=" << name;
+ map_fingerprint_target_.emplace(fingerprint, target);
+ map_name_fingerprint_.emplace(name, fingerprint);
+ }
+
+ public:
+ TargetFactoryImp() = default;
+ TargetFactoryImp(const TargetFactoryImp&) = delete;
+ TargetFactoryImp& operator=(const TargetFactoryImp&) = delete;
+
+ private:
+ std::map<std::uint64_t, const Target> map_fingerprint_target_;
+ std::map<std::string, std::uint64_t> map_name_fingerprint_;
+};
+
+static std::unique_ptr<std::vector<std::string>> get_target_prototxt_list() {
+ auto ret = std::make_unique<std::vector<std::string>>();
+ for (auto target_proto : TARGET_PROTOTXTS) {
+ ret->emplace_back(std::string(target_proto));
+ }
+ return ret;
+}
+
+static void register_targets(TargetFactoryImp* factory) {
+ GOOGLE_PROTOBUF_VERIFY_VERSION;
+ auto target_prototxt_list = get_target_prototxt_list();
+ for (auto& target_prototxt : *target_prototxt_list) {
+ Target target;
+ UNI_LOG_CHECK(
+ google::protobuf::TextFormat::ParseFromString(target_prototxt, &target),
+ TARGET_FACTORY_PARSE_TARGET_FAIL)
+ << "Cannot parse prototxt: \n"
+ << target_prototxt;
+ UNI_LOG_CHECK(target.name() != "" && target.type() != "",
+ TARGET_FACTORY_PARSE_TARGET_FAIL)
+ << "Uninitialized name or type";
+ factory->register_h(target);
+ }
+}
+
+const TargetFactory* target_factory() {
+ static std::once_flag register_once_flag;
+ static TargetFactoryImp self;
+ std::call_once(register_once_flag, register_targets, &self);
+ return &self;
+}
+
+const std::string TargetFactory::get_lib_name() {
+ const auto ret =
+ std::string{PROJECT_NAME} + "." + std::string{PROJECT_VERSION};
+ return ret;
+}
+
+const std::string TargetFactory::get_lib_id() {
+ const auto ret = std::string{PROJECT_GIT_COMMIT_ID};
+ return ret;
+}
+
+} // namespace ai
+} // namespace vitis
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#pragma once
+
+@TARGET_PROTOTXT_CODE@
+typedef const char * const_char_p;
+static constexpr const_char_p TARGET_PROTOTXTS[] = {@TARGET_PROTOTXTS@};
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# http://www.apache.org/licenses/LICENSE-2.0
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCADF8H_ISA0"
+type: "DPUCADF8H"
+isa_version: 0x00
+feature_code: 0x000000000000
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 16
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "CONVW"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "CONVW"
+ output_bank_group {
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ }
+ channel_augmentation {
+ channel_num : 16
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: prelu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ pool_type: max
+ max_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+ pool_type: avg
+ avg_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+dwconv_engine {
+ channel_parallel: 64
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ weight_bank: "CONVW"
+ bias_bank: "CONVW"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: prelu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ }
+}
+batch: 4
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCAHX8H_ISA2"
+type: "DPUCAHX8H"
+isa_version: 0x02
+feature_code: 0x00000010002a
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num : 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCAHX8H_ISA2_DWC"
+type: "DPUCAHX8H"
+isa_version: 0x02
+feature_code: 0x00000010002b
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVB"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVB"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 256
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "CONVB"
+ channel_augmentation {
+ channel_num : 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+}
+dwconv_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCONVB"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1,2,3,5,7"
+ stride: "1-4"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCAHX8H_ISA2_ELP2"
+type: "DPUCAHX8H"
+isa_version: 0x02
+feature_code: 0x00000000002e
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num : 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCAHX8L_ISA0"
+type: "DPUCAHX8L"
+isa_version: 0x00
+feature_code: 0x1d
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 32
+ bank_depth: 8388608
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 32
+ bank_depth: 8388608
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 4
+ bank_width: 32
+ bank_depth: 8388608
+}
+bank_group {
+ name: "VB3"
+ type: "Virtual"
+ base_id: 12
+ bank_num: 4
+ bank_width: 32
+ bank_depth: 8388608
+}
+bank_group {
+ name: "CB"
+ type: "Special"
+ base_id: 16
+ bank_num: 4
+ bank_width: 64
+ bank_depth: 4096
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 20
+ bank_num: 64
+ bank_width: 32
+ bank_depth: 4096
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 84
+ bank_num: 1
+ bank_width: 64
+ bank_depth: 4096
+}
+bank_group {
+ name: "CONVB"
+ type: "Param"
+ base_id: 85
+ bank_num: 1
+ bank_width: 64
+ bank_depth: 4096
+}
+bank_group {
+ name: "DWCONVB"
+ type: "Param"
+ base_id: 86
+ bank_num: 1
+ bank_width: 64
+ bank_depth: 4096
+}
+load_engine {
+ channel_parallel: 32
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ output_bank: "CB"
+}
+save_engine {
+ channel_parallel: 32
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+}
+conv_engine {
+ input_channel_parallel: 32
+ output_channel_parallel: 64
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ output_bank: "CB"
+ weight_bank: "CONVW"
+ bias_bank: "CONVB"
+ output_bank_group {
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ }
+ output_bank_group {
+ output_bank: "CB"
+ }
+ channel_augmentation {
+ channel_num : 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 32
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 32
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "2,3,5,7,8"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "2,3,5,7,8"
+ stride: "1-8"
+ }
+}
+dwconv_engine {
+ channel_parallel: 64
+ pixel_parallel: 4
+ input_bank: "CB"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCONVB"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "3"
+ stride: "1-2"
+ }
+}
+move_engine {
+ input_channel_parallel: 32
+ output_channel_parallel: 64
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+ output_bank: "CB"
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCAHX8L_ISA0_SP"
+type: "DPUCAHX8L"
+isa_version: 0x00
+feature_code: 0x101d
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 32
+ bank_depth: 8388608
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 32
+ bank_depth: 8388608
+}
+bank_group {
+ name: "VB2"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 4
+ bank_width: 32
+ bank_depth: 8388608
+}
+bank_group {
+ name: "VB3"
+ type: "Virtual"
+ base_id: 12
+ bank_num: 4
+ bank_width: 32
+ bank_depth: 8388608
+}
+bank_group {
+ name: "CB"
+ type: "Special"
+ base_id: 16
+ bank_num: 4
+ bank_width: 64
+ bank_depth: 4096
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 20
+ bank_num: 64
+ bank_width: 32
+ bank_depth: 4096
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 84
+ bank_num: 1
+ bank_width: 64
+ bank_depth: 4096
+}
+bank_group {
+ name: "CONVB"
+ type: "Param"
+ base_id: 85
+ bank_num: 1
+ bank_width: 64
+ bank_depth: 4096
+}
+bank_group {
+ name: "DWCONVB"
+ type: "Param"
+ base_id: 86
+ bank_num: 1
+ bank_width: 64
+ bank_depth: 4096
+}
+load_engine {
+ channel_parallel: 32
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ output_bank: "CB"
+}
+save_engine {
+ channel_parallel: 32
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+}
+conv_engine {
+ input_channel_parallel: 32
+ output_channel_parallel: 64
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ output_bank: "CB"
+ weight_bank: "CONVW"
+ bias_bank: "CONVB"
+ output_bank_group {
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ }
+ output_bank_group {
+ output_bank: "CB"
+ }
+ channel_augmentation {
+ channel_num : 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 32
+ pixel_parallel: 1
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 32
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "2,3,5,6,7,8"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "2,3,5,6,7,8"
+ stride: "1-8"
+ }
+}
+dwconv_engine {
+ channel_parallel: 64
+ pixel_parallel: 4
+ input_bank: "CB"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ output_bank: "VB2"
+ output_bank: "VB3"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCONVB"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "3,5"
+ stride: "1-2"
+ }
+}
+move_engine {
+ input_channel_parallel: 32
+ output_channel_parallel: 64
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ input_bank: "VB2"
+ input_bank: "VB3"
+ output_bank: "CB"
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA3_C32B1"
+type: "DPUCVDX8G"
+isa_version: 0x03
+feature_code: 0x000b16011811
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-2"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 1
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA3_C32B3"
+type: "DPUCVDX8G"
+isa_version: 0x03
+feature_code: 0x000b16011831
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-2"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA3_C32B3_PSMNET"
+type: "DPUCVDX8G"
+isa_version: 0x03
+feature_code: 0x000b16026831
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 16384
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-2"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA3_C32B6"
+type: "DPUCVDX8G"
+isa_version: 0x03
+feature_code: 0x000b16011861
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 32
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-2"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 6
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA3_C64B1"
+type: "DPUCVDX8G"
+isa_version: 0x03
+feature_code: 0x000b16011812
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 64
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-2"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 1
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA3_C64B3"
+type: "DPUCVDX8G"
+isa_version: 0x03
+feature_code: 0x000b16011832
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 64
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-2"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 3
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8G_ISA3_C64B5"
+type: "DPUCVDX8G"
+isa_version: 0x03
+feature_code: 0x000b16011852
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 8192
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCVBIAS"
+ type: "Param"
+ base_id: 34
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 64
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-8"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCVBIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-2"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
+batch: 5
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8H_ISA1_F2W2_8PE"
+type: "DPUCVDX8H"
+isa_version: 0x01
+feature_code: 0x140fee
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 128
+ bank_width: 64
+ bank_depth: 256
+}
+bank_group {
+ name: "CONVB"
+ type: "Param"
+ base_id: 144
+ bank_num: 1
+ bank_width: 128
+ bank_depth: 1024
+}
+load_engine {
+ channel_parallel: 64
+ output_bank: "VB0"
+ output_bank: "VB1"
+ load_mode {
+ src_type: ddr
+ src_type: imm
+ }
+}
+save_engine {
+ channel_parallel: 128
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 64
+ output_channel_parallel: 128
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "CONVB"
+ channel_augmentation {
+ channel_num: 64
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ conv_cascade {
+ pixel_parallel: 8
+ }
+}
+pool_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-3,7"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "1-3,7"
+ stride: "1-8"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8H_ISA1_F2W4_4PE"
+type: "DPUCVDX8H"
+isa_version: 0x01
+feature_code: 0x1e082f
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 128
+ bank_width: 64
+ bank_depth: 512
+}
+bank_group {
+ name: "CONVB"
+ type: "Param"
+ base_id: 144
+ bank_num: 1
+ bank_width: 128
+ bank_depth: 1024
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 145
+ bank_num: 1
+ bank_width: 32
+ bank_depth: 8192
+}
+bank_group {
+ name: "DWCONVB"
+ type: "Param"
+ base_id: 146
+ bank_num: 1
+ bank_width: 32
+ bank_depth: 128
+}
+load_engine {
+ channel_parallel: 64
+ output_bank: "VB0"
+ output_bank: "VB1"
+ load_mode {
+ src_type: ddr
+ src_type: imm
+ }
+}
+save_engine {
+ channel_parallel: 128
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 64
+ output_channel_parallel: 128
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "CONVB"
+ channel_augmentation {
+ channel_num: 64
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: hsigmoid
+ }
+ elew_type: add
+ elew_type: mult
+}
+pool_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-128"
+ stride: "1-128"
+ }
+ max_limit {
+ kernel_size: "1-128"
+ stride: "1-128"
+ }
+}
+dwconv_engine {
+ channel_parallel: 64
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCONVB"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8H_ISA1_F2W4_6PE_aieDWC"
+type: "DPUCVDX8H"
+isa_version: 0x01
+feature_code: 0x160c2f
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 128
+ bank_width: 64
+ bank_depth: 512
+}
+bank_group {
+ name: "CONVB"
+ type: "Param"
+ base_id: 144
+ bank_num: 1
+ bank_width: 128
+ bank_depth: 1024
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 145
+ bank_num: 1
+ bank_width: 32
+ bank_depth: 8192
+}
+bank_group {
+ name: "DWCONVB"
+ type: "Param"
+ base_id: 146
+ bank_num: 1
+ bank_width: 32
+ bank_depth: 128
+}
+load_engine {
+ channel_parallel: 64
+ output_bank: "VB0"
+ output_bank: "VB1"
+ load_mode {
+ src_type: ddr
+ src_type: imm
+ }
+}
+save_engine {
+ channel_parallel: 128
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 64
+ output_channel_parallel: 128
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "CONVB"
+ channel_augmentation {
+ channel_num: 64
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ conv_cascade {
+ pixel_parallel: 8
+ }
+}
+pool_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+ max_limit {
+ kernel_size: "1-8"
+ stride: "1-8"
+ }
+}
+dwconv_engine {
+ channel_parallel: 64
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "DWCONVB"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ dwconv_limit {
+ kernel_size: "1-8"
+ stride: "1-4"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+
+# http://www.apache.org/licenses/LICENSE-2.0
+
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCVDX8H_ISA1_F2W4_6PE_aieMISC"
+type: "DPUCVDX8H"
+isa_version: 0x01
+feature_code: 0x1e082e
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 64
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 128
+ bank_width: 64
+ bank_depth: 512
+}
+bank_group {
+ name: "CONVB"
+ type: "Param"
+ base_id: 144
+ bank_num: 1
+ bank_width: 128
+ bank_depth: 1024
+}
+load_engine {
+ channel_parallel: 64
+ output_bank: "VB0"
+ output_bank: "VB1"
+ load_mode {
+ src_type: ddr
+ src_type: imm
+ }
+}
+save_engine {
+ channel_parallel: 128
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 64
+ output_channel_parallel: 128
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "CONVB"
+ channel_augmentation {
+ channel_num: 64
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ nonlinear_type: leaky_relu
+ nonlinear_type: hsigmoid
+ nonlinear_type: hswish
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: hsigmoid
+ }
+ elew_type: add
+ elew_type: mult
+}
+pool_engine {
+ channel_parallel: 64
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ pool_type: max
+ pool_type: avg
+ nonlinear {}
+ avg_limit {
+ kernel_size: "1-128"
+ stride: "1-128"
+ }
+ max_limit {
+ kernel_size: "1-128"
+ stride: "1-128"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDI4G_ISA0_B4096_DEMO_SSD"
+type: "DPUCZDI4G"
+isa_version: 0x00
+feature_code: 0x002003220206
+bank_group {
+ name: "CB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+ word_width: 4
+ cyclic: true
+ adjustable_word_width {
+ scale: 8
+ word_width_switch: DataBit_x_BankDepth
+ }
+}
+bank_group {
+ name: "CB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+ word_width: 4
+ cyclic: true
+ adjustable_word_width {
+ scale: 8
+ word_width_switch: DataBit_x_BankDepth
+ }
+}
+bank_group {
+ name: "CB2"
+ type: "Virtual"
+ base_id: 16
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+ word_width: 4
+ cyclic: true
+ adjustable_word_width {
+ scale: 8
+ word_width_switch: DataBit_x_BankDepth
+ }
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 2048
+ word_width: 4
+ cyclic: true
+}
+bank_group {
+ name: "CONVB"
+ type: "Param"
+ base_id: 40
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+ word_width: 8
+ cyclic: true
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ output_bank: "CONVW"
+ output_bank: "CONVB"
+ fix_ifm_port_width {
+ port_width: 128
+ }
+ weight_split {
+ wgt_split: true
+ }
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ fix_ifm_port_width {
+ port_width: 128
+ }
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ weight_bank: "CONVW"
+ bias_bank: "CONVB"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ conv_limit {
+ kernel_size: "1-7"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+ pool_type: max_reduce
+}
+threshold_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ param_bank: "CONVB"
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDI4G_ISA0_B8192D8_DEMO_SSD"
+type: "DPUCZDI4G"
+isa_version: 0x00
+feature_code: 0x002003220207
+bank_group {
+ name: "CB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+ word_width: 4
+ cyclic: true
+ adjustable_word_width {
+ scale: 8
+ word_width_switch: DataBit_x_BankDepth
+ }
+}
+bank_group {
+ name: "CB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+ word_width: 4
+ cyclic: true
+ adjustable_word_width {
+ scale: 8
+ word_width_switch: DataBit_x_BankDepth
+ }
+}
+bank_group {
+ name: "CB2"
+ type: "Virtual"
+ base_id: 16
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+ word_width: 4
+ cyclic: true
+ adjustable_word_width {
+ scale: 8
+ word_width_switch: DataBit_x_BankDepth
+ }
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 16
+ bank_width: 32
+ bank_depth: 2048
+ word_width: 4
+ cyclic: true
+}
+bank_group {
+ name: "CONVB"
+ type: "Param"
+ base_id: 40
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+ word_width: 8
+ cyclic: true
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ output_bank: "CONVW"
+ output_bank: "CONVB"
+ fix_ifm_port_width {
+ port_width: 128
+ }
+ weight_split {
+ wgt_split: true
+ }
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ fix_ifm_port_width {
+ port_width: 128
+ }
+}
+conv_engine {
+ input_channel_parallel: 32
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ weight_bank: "CONVW"
+ bias_bank: "CONVB"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ conv_limit {
+ kernel_size: "1-7"
+ stride: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+}
+pool_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ pool_type: max
+ max_limit {
+ kernel_size: "2-8"
+ stride: "1-4"
+ }
+ pool_type: max_reduce
+}
+threshold_engine {
+ channel_parallel: 16
+ pixel_parallel: 2
+ input_bank: "CB0"
+ input_bank: "CB1"
+ input_bank: "CB2"
+ output_bank: "CB0"
+ output_bank: "CB1"
+ output_bank: "CB2"
+ param_bank: "CONVB"
+}
+batch: 1
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA1_B1024"
+type: "DPUCZDX8G"
+isa_version: 0x01
+feature_code: 0x000016010402
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 24
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 25
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 8
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 8
+ output_channel_parallel: 8
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 16
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 8
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 8
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-4"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA1_B1152"
+type: "DPUCZDX8G"
+isa_version: 0x01
+feature_code: 0x000016010203
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 8
+ bank_num: 12
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 20
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 21
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 12
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 12
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 12
+ output_channel_parallel: 12
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 24
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 12
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 12
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-4"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA1_B1600"
+type: "DPUCZDX8G"
+isa_version: 0x01
+feature_code: 0x000016010404
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 10
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 26
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 27
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 10
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 10
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 10
+ output_channel_parallel: 10
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 20
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 10
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 10
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-4"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA1_B2304"
+type: "DPUCZDX8G"
+isa_version: 0x01
+feature_code: 0x000016010405
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 12
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 28
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 29
+ bank_num: 1
+ bank_width: 12
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 12
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 12
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 12
+ output_channel_parallel: 12
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 24
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 12
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 12
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-4"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA1_B3136"
+type: "DPUCZDX8G"
+isa_version: 0x01
+feature_code: 0x000016010406
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 14
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 30
+ bank_num: 1
+ bank_width: 14
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 31
+ bank_num: 1
+ bank_width: 14
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 14
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 14
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 14
+ output_channel_parallel: 14
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 28
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 14
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 14
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-4"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA1_B4096"
+type: "DPUCZDX8G"
+isa_version: 0x01
+feature_code: 0x000016010407
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 8
+ bank_num: 8
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 16
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 32
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 33
+ bank_num: 1
+ bank_width: 16
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 16
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 16
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 16
+ output_channel_parallel: 16
+ pixel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 32
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 16
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-4"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA1_B512"
+type: "DPUCZDX8G"
+isa_version: 0x01
+feature_code: 0x000016010200
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 8
+ bank_num: 8
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 16
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 17
+ bank_num: 1
+ bank_width: 8
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 8
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 8
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 8
+ output_channel_parallel: 8
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 16
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 8
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 8
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-4"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+name: "DPUCZDX8G_ISA1_B800"
+type: "DPUCZDX8G"
+isa_version: 0x01
+feature_code: 0x000016010201
+bank_group {
+ name: "VB0"
+ type: "Virtual"
+ base_id: 0
+ bank_num: 4
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "VB1"
+ type: "Virtual"
+ base_id: 4
+ bank_num: 4
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "CONVW"
+ type: "Param"
+ base_id: 8
+ bank_num: 10
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "DWCONVW"
+ type: "Param"
+ base_id: 18
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+bank_group {
+ name: "BIAS"
+ type: "Param"
+ base_id: 19
+ bank_num: 1
+ bank_width: 10
+ bank_depth: 2048
+}
+load_engine {
+ channel_parallel: 10
+ output_bank: "VB0"
+ output_bank: "VB1"
+}
+save_engine {
+ channel_parallel: 10
+ input_bank: "VB0"
+ input_bank: "VB1"
+}
+conv_engine {
+ input_channel_parallel: 10
+ output_channel_parallel: 10
+ pixel_parallel: 4
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "CONVW"
+ bias_bank: "BIAS"
+ channel_augmentation {
+ channel_num: 20
+ }
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: leaky_relu
+ nonlinear_type: relu_six
+ }
+ conv_limit {
+ kernel_size: "1-16"
+ stride: "1-8"
+ stride_out_h: "1-4"
+ }
+}
+eltwise_engine {
+ channel_parallel: 10
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ nonlinear {
+ nonlinear_type: relu
+ }
+ elew_type: add
+ elew_type: mult
+}
+alu_engine {
+ channel_parallel: 10
+ pixel_parallel: 2
+ input_bank: "VB0"
+ input_bank: "VB1"
+ output_bank: "VB0"
+ output_bank: "VB1"
+ weight_bank: "DWCONVW"
+ bias_bank: "BIAS"
+ alu_type: dwconv
+ alu_type: prelu
+ alu_type: avg_pool
+ alu_type: max_pool
+ alu_type: leaky_relu
+ alu_type: max_reduce
+ alu_type: dwconv_no_bias
+ alu_type: hsigmoid
+ alu_type: w16b0
+ nonlinear {
+ nonlinear_type: relu
+ nonlinear_type: relu_six
+ }
+ alu_limit {
+ kernel_size: "1-256"
+ stride: "1-256"
+ stride_out_h: "1-4"
+ }
+ pad_limit {
+ pad_left: "0-15"
+ pad_right: "0-255"
+ pad_top: "0-15"
+ pad_bottom: "0-255"
+ }
+}
--- /dev/null
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+include_directories(${CMAKE_BINARY_DIR}/src)
+
+add_executable(test_factory test_factory.cpp)
+target_link_libraries(test_factory ${PROJECT_NAME} protobuf::libprotobuf unilog::unilog)
+
+add_executable(test_fingerprint test_fingerprint.cpp)
+target_link_libraries(test_fingerprint ${PROJECT_NAME} protobuf::libprotobuf unilog::unilog)
+
+add_executable(test_lib_info test_lib_info.cpp)
+target_link_libraries(test_lib_info ${PROJECT_NAME} unilog::unilog)
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "UniLog/UniLog.hpp"
+#include "vitis/ai/target_factory.hpp"
+
+#include <iomanip>
+#include <iostream>
+#include <string>
+using namespace vitis::ai;
+using namespace std;
+int main(int, char* argv[]) {
+ UniLog::Initial(argv[0], UNI_LOG_STD, UNI_LOG_LEVEL_INFO,
+ UNI_LOG_STD_LEVEL_INFO);
+ auto name = std::string{argv[1]};
+ auto target = target_factory()->create(name);
+ UNI_LOG_INFO << "Create target " << target.name();
+ UNI_LOG_INFO << " type " << target.type();
+ UNI_LOG_INFO << " isa version 0x" << std::hex << std::setw(2)
+ << setfill('0') << target.isa_version();
+ UNI_LOG_INFO << " feature code 0x" << std::hex << std::setw(12)
+ << setfill('0') << target.feature_code();
+ UNI_LOG_INFO << " fingerprint 0x" << std::hex << std::setw(16)
+ << setfill('0')
+ << target_factory()->get_fingerprint(target.name());
+ target_factory()->dump(target, "tmp.txt");
+ std::cout << "Dump target " << name << " to tmp.txt" << std::endl;
+
+ return 0;
+}
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "UniLog/UniLog.hpp"
+#include "vitis/ai/target_factory.hpp"
+
+#include <iomanip>
+#include <iostream>
+#include <string>
+
+using namespace vitis::ai;
+using namespace std;
+int main(int, char* argv[]) {
+ UniLog::Initial(argv[0], UNI_LOG_STD, UNI_LOG_LEVEL_INFO,
+ UNI_LOG_STD_LEVEL_INFO);
+
+ uint64_t fingerprint = std::stoull(argv[1], 0, 16);
+ auto target = target_factory()->create(fingerprint);
+ UNI_LOG_INFO << "Create target " << target.name();
+ UNI_LOG_INFO << " type " << target.type();
+ UNI_LOG_INFO << " isa version 0x" << std::hex << std::setw(2)
+ << setfill('0') << target.isa_version();
+ UNI_LOG_INFO << " feature code 0x" << std::hex << std::setw(12)
+ << setfill('0') << target.feature_code();
+ UNI_LOG_INFO << " fingerprint 0x" << std::hex << std::setw(16)
+ << setfill('0') << fingerprint;
+
+ target_factory()->dump(target, "./tmp");
+ std::cout << "Dump target " << target.name() << " to ./tmp" << std::endl;
+
+ return 0;
+}
--- /dev/null
+/*
+Copyright 2019 Xilinx Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+*/
+
+#include "UniLog/UniLog.hpp"
+#include "vitis/ai/target_factory.hpp"
+
+using namespace vitis::ai;
+
+int main(int, char* argv[]) {
+ UniLog::Initial(argv[0], UNI_LOG_STD, UNI_LOG_LEVEL_INFO,
+ UNI_LOG_STD_LEVEL_INFO);
+
+ UNI_LOG_INFO << "lib_name = " << TargetFactory::get_lib_name();
+ UNI_LOG_INFO << "lib_id = " << TargetFactory::get_lib_id();
+
+ return 0;
+}
projects / target-factory.git / commitdiff