Fix native backtraces on arm*

Author: Jacques-Henri Jourdan
Bug: http://caml.inria.fr/mantis/view.php?id=6233
Signed-off-by: Stephane Glondu <steph@glondu.net>
Gbp-Pq: Name 0015-Fix-native-backtraces-on-arm.patch

diff --git a/asmcomp/linearize.ml b/asmcomp/linearize.ml
index 963ffe9a2d04ef5f9695525c5f4f2a3df093dd8d..5095c3abebdc198eea7fa877d3601e6ace6e467b 100644 (file)
--- a/asmcomp/linearize.ml
+++ b/asmcomp/linearize.ml
@@ -86,6 +86,12 @@ let instr_cons d a r n =
   { desc = d; next = n; arg = a; res = r;
     dbg = Debuginfo.none; live = Reg.Set.empty }
 
+(* Cons an instruction (live empty) *)
+
+let instr_cons_debug d a r dbg n =
+ { desc = d; next = n; arg = a; res = r;
+ dbg = dbg; live = Reg.Set.empty }
+
 (* Cons a simple instruction (arg, res, live empty) *)
 
 let cons_instr d n =

diff --git a/asmcomp/linearize.mli b/asmcomp/linearize.mli
index ad5dc3a9fa61817ed6777078f42e611f8a98f2eb..ca203a777a6264f97363d6009a752c9f09028098 100644 (file)
--- a/asmcomp/linearize.mli
+++ b/asmcomp/linearize.mli
@@ -42,6 +42,9 @@ val has_fallthrough :  instruction_desc -> bool
 val end_instr: instruction
 val instr_cons:
   instruction_desc -> Reg.t array -> Reg.t array -> instruction -> instruction
+val instr_cons_debug:
+ instruction_desc -> Reg.t array -> Reg.t array -> Debuginfo.t ->
+ instruction -> instruction
 val invert_test: Mach.test -> Mach.test
 
 type fundecl =

diff --git a/asmcomp/schedgen.ml b/asmcomp/schedgen.ml
index 885c945404d5d3405764bff174ec53285cbd6b38..a04ab2733880b6623a337867e5f9dcb2e2a2c113 100644 (file)
--- a/asmcomp/schedgen.ml
+++ b/asmcomp/schedgen.ml
@@ -336,7 +336,8 @@ method private reschedule ready_queue date cont =
             if son.emitted_ancestors = son.ancestors then
               new_queue := son :: !new_queue)
           node.sons;
-        instr_cons node.instr.desc node.instr.arg node.instr.res
+        instr_cons_debug node.instr.desc node.instr.arg node.instr.res
+        node.instr.dbg
           (self#reschedule !new_queue (date + issue_cycles) cont)
   end