#define scif_writew(uart, off, val) writew((val), (uart)->regs + (off))
static struct scif_uart {
- unsigned int data_bits, parity, stop_bits;
unsigned int irq;
char __iomem *regs;
struct irqaction irqaction;
static void __init scif_uart_init_preirq(struct serial_port *port)
{
struct scif_uart *uart = port->uart;
- uint16_t val;
/*
* Wait until last bit has been transmitted. This is needed for a smooth
scif_readw(uart, SCIF_SCLSR);
scif_writew(uart, SCIF_SCLSR, 0);
- /* Select Baud rate generator output as a clock source */
- scif_writew(uart, SCIF_SCSCR, SCSCR_CKE10);
-
- /* Setup protocol format and Baud rate, select Asynchronous mode */
- val = 0;
- ASSERT( uart->data_bits >= 7 && uart->data_bits <= 8 );
- if ( uart->data_bits == 7 )
- val |= SCSMR_CHR;
- else
- val &= ~SCSMR_CHR;
-
- ASSERT( uart->stop_bits >= 1 && uart->stop_bits <= 2 );
- if ( uart->stop_bits == 2 )
- val |= SCSMR_STOP;
- else
- val &= ~SCSMR_STOP;
-
- ASSERT( uart->parity >= PARITY_NONE && uart->parity <= PARITY_ODD );
- switch ( uart->parity )
- {
- case PARITY_NONE:
- val &= ~SCSMR_PE;
- break;
-
- case PARITY_EVEN:
- val |= SCSMR_PE;
- break;
-
- case PARITY_ODD:
- val |= SCSMR_PE | SCSMR_ODD;
- break;
- }
- scif_writew(uart, SCIF_SCSMR, val);
-
/* Setup trigger level for TX/RX FIFOs */
scif_writew(uart, SCIF_SCFCR, SCFCR_RTRG11 | SCFCR_TTRG11);
uart = &scif_com;
- uart->data_bits = 8;
- uart->parity = PARITY_NONE;
- uart->stop_bits = 1;
-
res = dt_device_get_address(dev, 0, &addr, &size);
if ( res )
{