{
switch ( cpu_model )
{
- case 15:
- case 23:
- case 26:
- case 29:
- case 42:
- case 45:
- case 46:
- case 47:
- case 58:
- case 62:
+ case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
+ case 23: /* 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
+ case 26: /* 45 nm nehalem, "Bloomfield" */
+ case 29: /* six-core 45 nm xeon "Dunnington" */
+ case 42: /* SandyBridge */
+ case 45: /* SandyBridge, "Romley-EP" */
+ case 46: /* 45 nm nehalem-ex, "Beckton" */
+ case 47: /* 32 nm Xeon E7 */
+ case 58: /* IvyBridge */
+ case 62: /* IvyBridge EP */
ret = core2_vpmu_initialise(v, vpmu_flags);
if ( !ret )
vpmu->arch_vpmu_ops = &core2_vpmu_ops;