uint32_t pci_min, pci_len; /* 4, 8 - PCI I/O hole boundaries */
uint32_t madt_csum_addr; /* 12 - Address of MADT checksum */
uint32_t madt_lapic0_addr; /* 16 - Address of first MADT LAPIC struct */
+ uint32_t vm_gid_addr; /* 20 - Address of VM generation id buffer */
};
/* Number of processor objects in the chosen DSDT. */
PMIN, 32,
PLEN, 32,
MSUA, 32, /* MADT checksum address */
- MAPA, 32 /* MADT LAPIC0 address */
+ MAPA, 32, /* MADT LAPIC0 address */
+ VGIA, 32 /* VM generation id address */
}
/* Fix HCT test for 0x400 pci memory:
IRQNoFlags () {7}
})
}
+
+ Device(VGID) {
+ Name(_HID, EisaID ("PNP0A06"))
+ Name(_UID, 0x00)
+ Name(_CID, "VM_Gen_Counter")
+ Name(_DDN, "VM_Gen_Counter")
+ Method(_STA, 0, NotSerialized)
+ {
+ If(LEqual(\_SB.VGIA, 0x00000000)) {
+ Return(0x00)
+ } Else {
+ Return(0x0F)
+ }
+ }
+ Name(PKG, Package ()
+ {
+ 0x00000000,
+ 0x00000000
+ })
+ Method(ADDR, 0, NotSerialized)
+ {
+ Store(\_SB.VGIA, Index(PKG, 0))
+ Return(PKG)
+ }
+ }
}
}
}