.update_ire_from_msi = amd_iommu_msi_msg_update_ire,
.read_apic_from_ire = amd_iommu_read_ioapic_from_ire,
.read_msi_from_ire = amd_iommu_read_msi_from_ire,
+ .suspend = amd_iommu_suspend,
+ .resume = amd_iommu_resume,
};
return ops->read_apic_from_ire(apic, reg);
}
+void iommu_resume()
+{
+ struct iommu_ops *ops = iommu_get_ops();
+ if ( iommu_enabled )
+ ops->resume();
+}
+
+void iommu_suspend()
+{
+ struct iommu_ops *ops = iommu_get_ops();
+ if ( iommu_enabled )
+ ops->suspend();
+}
+
/*
* Local variables:
* mode: C
}
static u32 iommu_state[MAX_IOMMUS][MAX_IOMMU_REGS];
-void iommu_suspend(void)
+void vtd_suspend(void)
{
struct acpi_drhd_unit *drhd;
struct iommu *iommu;
}
}
-void iommu_resume(void)
+void vtd_resume(void)
{
struct acpi_drhd_unit *drhd;
struct iommu *iommu;
.update_ire_from_msi = msi_msg_write_remap_rte,
.read_apic_from_ire = io_apic_read_remap_rte,
.read_msi_from_ire = msi_msg_read_remap_rte,
+ .suspend = vtd_suspend,
+ .resume = vtd_resume,
};
/*
unsigned int amd_iommu_read_ioapic_from_ire(
unsigned int apic, unsigned int reg);
+/* power management support */
+void amd_iommu_resume(void);
+void amd_iommu_suspend(void);
+
static inline u32 get_field_from_reg_u32(u32 reg_value, u32 mask, u32 shift)
{
u32 field;
void (*update_ire_from_msi)(struct msi_desc *msi_desc, struct msi_msg *msg);
void (*read_msi_from_ire)(struct msi_desc *msi_desc, struct msi_msg *msg);
unsigned int (*read_apic_from_ire)(unsigned int apic, unsigned int reg);
+ void (*suspend)(void);
+ void (*resume)(void);
};
void iommu_update_ire_from_apic(unsigned int apic, unsigned int reg, unsigned int value);