x86: Use deep C states for off-lined CPUs

Currently when a core is taken off-line it is placed in C1 state
(unless MONITOR/MWAIT is used). This patch allows a core to go to
deeper C states resulting in significantly higher power savings.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
Committed-by: Keir Fraser <keir@xen.org>

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index a675867f2450a4e15f26e6d802016c9989d4ae43..75593d146a4dba56dcdaba80ecb7e773c1a496ab 100644 (file)
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -566,6 +566,7 @@ static void acpi_dead_idle(void)
 {
     struct acpi_processor_power *power;
     struct acpi_processor_cx *cx;
+    struct cpuinfo_x86 *c = &current_cpu_data;
 
     if ( (power = processor_powers[smp_processor_id()]) == NULL )
         goto default_halt;
@@ -601,6 +602,23 @@ static void acpi_dead_idle(void)
             mb();
             __mwait(cx->address, 0);
         }
+    } 
+    else if ( c->x86_vendor == X86_VENDOR_AMD && 
+              cx->entry_method == ACPI_CSTATE_EM_SYSIO )
+    {
+        /* Intel prefers not to use SYSIO */
+
+        /* Avoid references to shared data after the cache flush */
+        u32 address = cx->address;
+        u32 pmtmr_ioport_local = pmtmr_ioport;
+
+        wbinvd();
+
+        while ( 1 )
+        {
+            inb(address);
+            inl(pmtmr_ioport_local);
+        }
     }
     else if ( current_cpu_data.x86_vendor == X86_VENDOR_AMD &&
               cx->entry_method == ACPI_CSTATE_EM_SYSIO )