x86/Intel: skip CORE_THREAD_COUNT read on family 0xf
authorJan Beulich <jbeulich@suse.com>
Mon, 14 Feb 2022 09:05:38 +0000 (10:05 +0100)
committerJan Beulich <jbeulich@suse.com>
Mon, 14 Feb 2022 09:05:38 +0000 (10:05 +0100)
This avoids an unnecessary (and always somewhat scary) log message for
the recovered from #GP(0).

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Roger Pau Monné <roger.pau@citrix.com>
xen/arch/x86/spec_ctrl.c

index cbeeb199037e893d5aab50c06f03444ae200692a..db27bc3f6451c81eeb5adf137d5bb222ebe3b6c8 100644 (file)
@@ -453,7 +453,8 @@ static bool __init check_smt_enabled(void)
      * At the time of writing, it is almost completely undocumented, so isn't
      * virtualised reliably.
      */
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && !cpu_has_hypervisor &&
+    if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+         boot_cpu_data.x86 != 0xf && !cpu_has_hypervisor &&
          !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, val) )
         return (MASK_EXTR(val, MSR_CTC_CORE_MASK) !=
                 MASK_EXTR(val, MSR_CTC_THREAD_MASK));