Revert "MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6"

This reverts commit 07d8aabff4903065bb472df9b040b8688fdc75a2 which was
commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream.  This
changed L1_CACHE_SHIFT which is used for structure alignment in many
places, thus would break ABI.

Gbp-Pq: Topic debian
Gbp-Pq: Name revert-mips-loongson-3-select-mips_l1_cache_shift_6.patch

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5e844f68e847976ffcaf295855851debf787188b..5a4f2eb9d0d5782aa0f0f15a0d04823c397e9021 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1368,7 +1368,6 @@ config CPU_LOONGSON3
        select WEAK_ORDERING
        select WEAK_REORDERING_BEYOND_LLSC
        select MIPS_PGD_C0_CONTEXT
-       select MIPS_L1_CACHE_SHIFT_6
        select GPIOLIB
        help
                The Loongson 3 processor implements the MIPS64R2 instruction