[IA64] Turn on dcr.dm inside XEN

For xeno, dcr.dm is alway set to 1,
For VTI-domain,
    if guest cpl > 0, dcr.dm is set to 1,
    if guest cpl == 0, dcr.dm is set to 0,
This is because Window ld.s on tr mapped page.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>

diff --git a/xen/arch/ia64/vmx/vmx_interrupt.c b/xen/arch/ia64/vmx/vmx_interrupt.c
index 211aa93b363e936d76ef032e2934e20a60b5bbd7..7dc4db744c03a61de6d65c802666a446e0cfcfd6 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_interrupt.c
+++ b/xen/arch/ia64/vmx/vmx_interrupt.c
@@ -99,7 +99,7 @@ inject_guest_interruption(VCPU *vcpu, u64 vec)
     pt_isr.ir = 0;
     VMX(vcpu,cr_isr) = pt_isr.val;
     collect_interruption(vcpu);
-
+    vmx_ia64_set_dcr(vcpu);
     vmx_vcpu_get_iva(vcpu,&viva);
     regs->cr_iip = viva + vec;
 }

diff --git a/xen/arch/ia64/vmx/vmx_phy_mode.c b/xen/arch/ia64/vmx/vmx_phy_mode.c
index ce4fd9036cc20beb41f5b40f09cbcc05e46f42f0..b6155aa6707e292f8422dc01ce9f58081c49eb93 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_phy_mode.c
+++ b/xen/arch/ia64/vmx/vmx_phy_mode.c
@@ -188,7 +188,7 @@ vmx_load_all_rr(VCPU *vcpu)
                        (void *)vcpu->arch.privregs,
                        (void *)vcpu->arch.vhpt.hash, pal_vaddr );
        ia64_set_pta(VMX(vcpu, mpta));
-       ia64_set_dcr(VMX(vcpu, mdcr));
+       vmx_ia64_set_dcr(vcpu);
 
        ia64_srlz_d();
        ia64_set_psr(psr);

diff --git a/xen/arch/ia64/vmx/vmx_vcpu.c b/xen/arch/ia64/vmx/vmx_vcpu.c
index f0418a89983304e666759b5670847e33ffa89fca..2dc2114db52d1ee691091aa7d54c2feb17c8ee4a 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_vcpu.c
+++ b/xen/arch/ia64/vmx/vmx_vcpu.c
@@ -78,6 +78,22 @@ struct guest_psr_bundle guest_psr_buf[100];
 unsigned long guest_psr_index = 0;
 #endif
 
+
+void
+vmx_ia64_set_dcr(VCPU *v)   
+{
+    unsigned long dcr_bits = IA64_DEFAULT_DCR_BITS;
+
+    // if guest is runing on cpl > 0, set dcr.dm=1
+    // if geust is runing on cpl = 0, set dcr.dm=0
+    // because Guest OS may ld.s on tr mapped page.
+    if (!(VCPU(v, vpsr) & IA64_PSR_CPL))
+        dcr_bits &= ~IA64_DCR_DM;
+
+    ia64_set_dcr(dcr_bits);
+}
+
+
 void
 vmx_vcpu_set_psr(VCPU *vcpu, unsigned long value)
 {
@@ -261,6 +277,7 @@ IA64FAULT vmx_vcpu_rfi(VCPU *vcpu)
     else
         vcpu_bsw0(vcpu);
     vmx_vcpu_set_psr(vcpu,psr);
+    vmx_ia64_set_dcr(vcpu);
     ifs=VCPU(vcpu,ifs);
     if(ifs>>63)
         regs->cr_ifs = ifs;

diff --git a/xen/arch/ia64/vmx/vmx_virt.c b/xen/arch/ia64/vmx/vmx_virt.c
index 9926c6ed8fe8a20a592ac978193ce982df7592be..57e155297182adf19282623de2b7c438dc7098e5 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_virt.c
+++ b/xen/arch/ia64/vmx/vmx_virt.c
@@ -1234,7 +1234,7 @@ IA64FAULT vmx_emul_mov_to_cr(VCPU *vcpu, INST64 inst)
 #endif  //CHECK_FAULT
     r2 = cr_igfld_mask(inst.M32.cr3,r2);
     switch (inst.M32.cr3) {
-        case 0: return vmx_vcpu_set_dcr(vcpu,r2);
+        case 0: return vcpu_set_dcr(vcpu,r2);
         case 1: return vmx_vcpu_set_itm(vcpu,r2);
         case 2: return vmx_vcpu_set_iva(vcpu,r2);
         case 8: return vmx_vcpu_set_pta(vcpu,r2);
@@ -1299,7 +1299,7 @@ IA64FAULT vmx_emul_mov_from_cr(VCPU *vcpu, INST64 inst)
 
 //    from_cr_cnt[inst.M33.cr3]++;
     switch (inst.M33.cr3) {
-        case 0: return vmx_cr_get(dcr);
+        case 0: return cr_get(dcr);
         case 1: return vmx_cr_get(itm);
         case 2: return vmx_cr_get(iva);
         case 8: return vmx_cr_get(pta);

diff --git a/xen/arch/ia64/xen/domain.c b/xen/arch/ia64/xen/domain.c
index 6b76df3e58d75502720a0f74da1ddc953ca8d0a2..9c21d0294955a38a10be87f8e6166d989507b59d 100644 (file)
--- a/xen/arch/ia64/xen/domain.c
+++ b/xen/arch/ia64/xen/domain.c
@@ -42,6 +42,7 @@
 #include <asm/vmx_vpd.h>
 #include <asm/vmx_phy_mode.h>
 #include <asm/vhpt.h>
+#include <asm/vcpu.h>
 #include <asm/tlbflush.h>
 #include <asm/regionreg.h>
 #include <asm/dom_fw.h>
@@ -204,9 +205,7 @@ void context_switch(struct vcpu *prev, struct vcpu *next)
         if (!VMX_DOMAIN(next)) {
             /* VMX domains can change the physical cr.dcr.
              * Restore default to prevent leakage. */
-            ia64_setreg(_IA64_REG_CR_DCR, (IA64_DCR_DP | IA64_DCR_DK
-                           | IA64_DCR_DX | IA64_DCR_DR | IA64_DCR_PP
-                           | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
+            ia64_setreg(_IA64_REG_CR_DCR, IA64_DEFAULT_DCR_BITS);
         }
     }
     if (VMX_DOMAIN(next))
@@ -582,7 +581,7 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c)
                er->dtrs[i].rid = v->arch.dtrs[i].rid;
        }
        er->event_callback_ip = v->arch.event_callback_ip;
-       er->dcr = v->arch.dcr;
+       er->dcr = PSCB(v,dcr);
        er->iva = v->arch.iva;
 }
 
@@ -618,7 +617,7 @@ int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
                                     er->dtrs[i].rid);
                }
                v->arch.event_callback_ip = er->event_callback_ip;
-               v->arch.dcr = er->dcr;
+               PSCB(v,dcr) = er->dcr;
                v->arch.iva = er->iva;
        }
 

diff --git a/xen/arch/ia64/xen/vcpu.c b/xen/arch/ia64/xen/vcpu.c
index bef5059b9fb8de88680352d271f163e1d41131a2..a21574ec2b9b984839ae3aa21e5cf0f80b0cde97 100644 (file)
--- a/xen/arch/ia64/xen/vcpu.c
+++ b/xen/arch/ia64/xen/vcpu.c
@@ -501,7 +501,7 @@ BOOLEAN vcpu_get_psr_i(VCPU * vcpu)
 
 u64 vcpu_get_ipsr_int_state(VCPU * vcpu, u64 prevpsr)
 {
-       u64 dcr = PSCBX(vcpu, dcr);
+       u64 dcr = PSCB(vcpu, dcr);
        PSR psr;
 
        //printk("*** vcpu_get_ipsr_int_state (0x%016lx)...\n",prevpsr);
@@ -532,10 +532,7 @@ u64 vcpu_get_ipsr_int_state(VCPU * vcpu, u64 prevpsr)
 
 IA64FAULT vcpu_get_dcr(VCPU * vcpu, u64 * pval)
 {
-//verbose("vcpu_get_dcr: called @%p\n",PSCB(vcpu,iip));
-       // Reads of cr.dcr on Xen always have the sign bit set, so
-       // a domain can differentiate whether it is running on SP or not
-       *pval = PSCBX(vcpu, dcr) | 0x8000000000000000L;
+       *pval = PSCB(vcpu, dcr);
        return IA64_NO_FAULT;
 }
 
@@ -651,11 +648,7 @@ IA64FAULT vcpu_get_iha(VCPU * vcpu, u64 * pval)
 
 IA64FAULT vcpu_set_dcr(VCPU * vcpu, u64 val)
 {
-       // Reads of cr.dcr on SP always have the sign bit set, so
-       // a domain can differentiate whether it is running on SP or not
-       // Thus, writes of DCR should ignore the sign bit
-//verbose("vcpu_set_dcr: called\n");
-       PSCBX(vcpu, dcr) = val & ~0x8000000000000000L;
+       PSCB(vcpu, dcr) = val;
        return IA64_NO_FAULT;
 }
 

diff --git a/xen/include/asm-ia64/domain.h b/xen/include/asm-ia64/domain.h
index ce734c8677524c7e149c10217aa7ccd63f4d73c7..66f9caec2e3b885b82103242f1089892f18ebfe0 100644 (file)
--- a/xen/include/asm-ia64/domain.h
+++ b/xen/include/asm-ia64/domain.h
@@ -162,7 +162,6 @@ struct arch_vcpu {
     unsigned long irr[4];          /* Interrupt request register.  */
     unsigned long insvc[4];            /* Interrupt in service.  */
     unsigned long iva;
-    unsigned long dcr;
     unsigned long domain_itm;
     unsigned long domain_itm_last;
 

diff --git a/xen/include/asm-ia64/vmx_vcpu.h b/xen/include/asm-ia64/vmx_vcpu.h
index 24b3b60578fd43b913d6288bc35a1e8350114619..fda5e82389930a23c08c1a30094de1cd5a02308d 100644 (file)
--- a/xen/include/asm-ia64/vmx_vcpu.h
+++ b/xen/include/asm-ia64/vmx_vcpu.h
@@ -126,17 +126,12 @@ extern void dnat_page_consumption(VCPU * vcpu, uint64_t vadr);
 extern void data_page_not_present(VCPU * vcpu, u64 vadr);
 extern void inst_page_not_present(VCPU * vcpu, u64 vadr);
 extern void data_access_rights(VCPU * vcpu, u64 vadr);
+extern void vmx_ia64_set_dcr(VCPU * v);
 
 /**************************************************************************
  VCPU control register access routines
 **************************************************************************/
 
-static inline IA64FAULT vmx_vcpu_get_dcr(VCPU * vcpu, u64 * pval)
-{
-       *pval = VCPU(vcpu, dcr);
-       return IA64_NO_FAULT;
-}
-
 static inline IA64FAULT vmx_vcpu_get_itm(VCPU * vcpu, u64 * pval)
 {
        *pval = VCPU(vcpu, itm);
@@ -233,20 +228,6 @@ static inline IA64FAULT vmx_vcpu_get_lrr1(VCPU * vcpu, u64 * pval)
        return IA64_NO_FAULT;
 }
 
-static inline IA64FAULT vmx_vcpu_set_dcr(VCPU * vcpu, u64 val)
-{
-       u64 mdcr, mask;
-       VCPU(vcpu, dcr) = val;
-       /* All vDCR bits will go to mDCR, except for be/pp/dm bits */
-       mdcr = ia64_get_dcr();
-       /* Machine dcr.dm masked to handle guest ld.s on tr mapped page */
-       mask = IA64_DCR_BE | IA64_DCR_PP | IA64_DCR_DM;
-       mdcr = (mdcr & mask) | (val & (~mask));
-       ia64_set_dcr(mdcr);
-       VMX(vcpu, mdcr) = mdcr;
-       return IA64_NO_FAULT;
-}
-
 static inline IA64FAULT vmx_vcpu_set_itm(VCPU * vcpu, u64 val)
 {
        vtm_set_itm(vcpu, val);

diff --git a/xen/include/asm-ia64/vmx_vpd.h b/xen/include/asm-ia64/vmx_vpd.h
index 8e4eb4f55c619881e08bbdbe3d845c64701f5839..e8876bb1544eea14755e9861c30f53812a7fc299 100644 (file)
--- a/xen/include/asm-ia64/vmx_vpd.h
+++ b/xen/include/asm-ia64/vmx_vpd.h
@@ -86,16 +86,7 @@ struct arch_vmx_struct {
     unsigned long   cr_isr;    /* for emulation */
     unsigned long   cause;
     unsigned long   opcode;
-
-//    unsigned long   mrr5;
-//    unsigned long   mrr6;
-//    unsigned long   mrr7;
-    unsigned long   mdcr;
     unsigned long   mpta;
-//    unsigned long   rfi_pfs;
-//    unsigned long   rfi_iip;
-//    unsigned long   rfi_ipsr;
-//    unsigned long   rfi_ifs;
     unsigned long   flags;
     unsigned long   xen_port;
     unsigned char   xtp;

diff --git a/xen/include/asm-ia64/xenkregs.h b/xen/include/asm-ia64/xenkregs.h
index d2dcd2bc84b1856a1b92fb28f674e0899b638de0..4050bb700f51acb284d64920b7dcac28a965e784 100644 (file)
--- a/xen/include/asm-ia64/xenkregs.h
+++ b/xen/include/asm-ia64/xenkregs.h
@@ -13,6 +13,10 @@
 #define IA64_PSR_VM_BIT                46
 #define IA64_PSR_VM    (__IA64_UL(1) << IA64_PSR_VM_BIT)
 
+#define IA64_DEFAULT_DCR_BITS  (IA64_DCR_PP | IA64_DCR_LC | IA64_DCR_DM | \
+                                IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | \
+                                IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD)
+
 /* Interruption Function State */
 #define IA64_IFS_V_BIT         63
 #define IA64_IFS_V     (__IA64_UL(1) << IA64_IFS_V_BIT)