Previous to this patch we would see in the trace file:
CPU28
1753503175371 (+ 8496) unknown (0x0000000000801002) [ 0x00000004 0x4158a498 0x000003a1 0x000027e6 0x00000000 0x00000000 0x00000000 ]
CPU28
1753505321239 (+
2145868) unknown (0x0000000000801003) [ 0x00000004 0x4166dca7 0x000000fa 0x00000000 0x00000000 0x00000000 0x00000000 ]
CPU28
1753505343756 (+ 22517) unknown (0x0000000000801002) [ 0x00000004 0x41670fe5 0x00001284 0x00003766 0x00000000 0x00000000 0x00000000 ]
CPU28
1753521413711 (+
16069955) unknown (0x0000000000801003) [ 0x00000004 0x41d1e02c 0x000000ab 0x00000000 0x00000000 0x00000000 0x00000000 ]
instead of:
CPU28
1753503175371 (+ 8496) cpu_idle_entry [ C0 -> C4, acpi_pm_tick =
1096328344, expected = 929us, predicted = 10214us ]
CPU28
1753505321239 (+
2145868) cpu_idle_exit [ C4 -> C0, acpi_pm_tick =
1097260199, irq = 250 0 0 0 ]
CPU28
1753505343756 (+ 22517) cpu_idle_entry [ C0 -> C4, acpi_pm_tick =
1097273317, expected = 4740us, predicted = 14182us ]
CPU28
1753521413711 (+
16069955) cpu_idle_exit [ C4 -> C0, acpi_pm_tick =
1104273452, irq = 171 0 0 0 ]
The patch that added the cpu_idle_[entry|exit] was using the
TRC_HW_IRQ class (0x00802000) instead of TRC_HW_PM (0x00801000)
as a base.
Acked-by: George Dunlap <george.dunlap@eu.citrix.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
0x0040f10f CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_resync_only [ gfn = 0x%(2)08x%(1)08x ]
0x00801001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) cpu_freq_change [ %(1)dMHz -> %(2)dMHz ]
-0x00802001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) cpu_idle_entry [ C0 -> C%(1)d, acpi_pm_tick = %(2)d, expected = %(3)dus, predicted = %(4)dus ]
-0x00802002 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) cpu_idle_exit [ C%(1)d -> C0, acpi_pm_tick = %(2)d, irq = %(3)d %(4)d %(5)d %(6)d ]
+0x00801002 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) cpu_idle_entry [ C0 -> C%(1)d, acpi_pm_tick = %(2)d, expected = %(3)dus, predicted = %(4)dus ]
+0x00801003 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) cpu_idle_exit [ C%(1)d -> C0, acpi_pm_tick = %(2)d, irq = %(3)d %(4)d %(5)d %(6)d ]