{
struct pt_regs *regs = (struct pt_regs *) &stack;
unsigned long code;
- static const char *reason[] = {
+ static const char * const reason[] = {
"IA-64 Illegal Operation fault",
"IA-64 Privileged Operation fault",
"IA-64 Privileged Register fault",
"IA-64 Reserved Register/Field fault",
"Disabled Instruction Set Transition fault",
- "Unknown fault 5", "Unknown fault 6", "Unknown fault 7", "Illegal Hazard fault",
- "Unknown fault 9", "Unknown fault 10", "Unknown fault 11", "Unknown fault 12",
+ "Unknown fault 5", "Unknown fault 6",
+ "Unknown fault 7", "Illegal Hazard fault",
+ "Unknown fault 9", "Unknown fault 10",
+ "Unknown fault 11", "Unknown fault 12",
"Unknown fault 13", "Unknown fault 14", "Unknown fault 15"
};
}
}
-/* Used in vhpt.h. */
-#define INTR_TYPE_MAX 10
-UINT64 int_counts[INTR_TYPE_MAX];
-
void
ia64_handle_reflection (unsigned long ifa, struct pt_regs *regs, unsigned long isr, unsigned long iim, unsigned long vector)
{
unsigned long psr = regs->cr_ipsr;
/* Following faults shouldn'g be seen from Xen itself */
- if (!(psr & IA64_PSR_CPL)) BUG();
+ BUG_ON (!(psr & IA64_PSR_CPL));
switch(vector) {
case 8:
break;
case 26:
if (((isr >> 4L) & 0xfL) == 1) {
+ /* Fault is due to a register NaT consumption fault. */
//regs->eml_unat = 0; FIXME: DO WE NEED THIS??
printf("ia64_handle_reflection: handling regNaT fault\n");
vector = IA64_NAT_CONSUMPTION_VECTOR; break;
vector = IA64_NAT_CONSUMPTION_VECTOR; break;
}
#endif
+#ifdef CONFIG_PRIVIFY
+ /* Some privified operations are coded using reg+64 instead
+ of reg. */
printf("*** NaT fault... attempting to handle as privop\n");
printf("isr=%016lx, ifa=%016lx, iip=%016lx, ipsr=%016lx\n",
isr, ifa, regs->cr_iip, psr);
printf("*** Handled privop masquerading as NaT fault\n");
return;
}
+#endif
vector = IA64_NAT_CONSUMPTION_VECTOR; break;
case 27:
//printf("*** Handled speculation vector, itc=%lx!\n",ia64_get_itc());
#include <asm/delay.h> // Debug only
#include <asm/dom_fw.h>
#include <asm/vhpt.h>
-//#include <debug.h>
/* FIXME: where these declarations should be there ? */
extern int dump_reflect_counts(char *);
long priv_verbose=0;
/* Set to 1 to handle privified instructions from the privify tool. */
+#ifndef CONFIG_PRIVIFY
static const int privify_en = 0;
+#else
+static const int privify_en = 1;
+#endif
/**************************************************************************
Hypercall bundle creation
**************************************************************************/
-
void build_hypercall_bundle(UINT64 *imva, UINT64 brkimm, UINT64 hypnum, UINT64 ret)
{
INST64_A5 slot0;
Privileged operation emulation routines
**************************************************************************/
-IA64FAULT priv_rfi(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_rfi(VCPU *vcpu, INST64 inst)
{
return vcpu_rfi(vcpu);
}
-IA64FAULT priv_bsw0(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_bsw0(VCPU *vcpu, INST64 inst)
{
return vcpu_bsw0(vcpu);
}
-IA64FAULT priv_bsw1(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_bsw1(VCPU *vcpu, INST64 inst)
{
return vcpu_bsw1(vcpu);
}
-IA64FAULT priv_cover(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_cover(VCPU *vcpu, INST64 inst)
{
return vcpu_cover(vcpu);
}
-IA64FAULT priv_ptc_l(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_ptc_l(VCPU *vcpu, INST64 inst)
{
UINT64 vadr = vcpu_get_gr(vcpu,inst.M45.r3);
UINT64 log_range;
return vcpu_ptc_l(vcpu,vadr,log_range);
}
-IA64FAULT priv_ptc_e(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_ptc_e(VCPU *vcpu, INST64 inst)
{
UINT src = inst.M28.r3;
return vcpu_ptc_e(vcpu,vcpu_get_gr(vcpu,src));
}
-IA64FAULT priv_ptc_g(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_ptc_g(VCPU *vcpu, INST64 inst)
{
UINT64 vadr = vcpu_get_gr(vcpu,inst.M45.r3);
UINT64 addr_range;
return vcpu_ptc_g(vcpu,vadr,addr_range);
}
-IA64FAULT priv_ptc_ga(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_ptc_ga(VCPU *vcpu, INST64 inst)
{
UINT64 vadr = vcpu_get_gr(vcpu,inst.M45.r3);
UINT64 addr_range;
return vcpu_ptc_ga(vcpu,vadr,addr_range);
}
-IA64FAULT priv_ptr_d(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_ptr_d(VCPU *vcpu, INST64 inst)
{
UINT64 vadr = vcpu_get_gr(vcpu,inst.M45.r3);
UINT64 log_range;
return vcpu_ptr_d(vcpu,vadr,log_range);
}
-IA64FAULT priv_ptr_i(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_ptr_i(VCPU *vcpu, INST64 inst)
{
UINT64 vadr = vcpu_get_gr(vcpu,inst.M45.r3);
UINT64 log_range;
return vcpu_ptr_i(vcpu,vadr,log_range);
}
-IA64FAULT priv_tpa(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_tpa(VCPU *vcpu, INST64 inst)
{
UINT64 padr;
UINT fault;
else return fault;
}
-IA64FAULT priv_tak(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_tak(VCPU *vcpu, INST64 inst)
{
UINT64 key;
UINT fault;
* Insert translation register/cache
************************************/
-IA64FAULT priv_itr_d(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_itr_d(VCPU *vcpu, INST64 inst)
{
UINT64 fault, itir, ifa, pte, slot;
return (vcpu_itr_d(vcpu,slot,pte,itir,ifa));
}
-IA64FAULT priv_itr_i(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_itr_i(VCPU *vcpu, INST64 inst)
{
UINT64 fault, itir, ifa, pte, slot;
return (vcpu_itr_i(vcpu,slot,pte,itir,ifa));
}
-IA64FAULT priv_itc_d(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_itc_d(VCPU *vcpu, INST64 inst)
{
UINT64 fault, itir, ifa, pte;
return (vcpu_itc_d(vcpu,pte,itir,ifa));
}
-IA64FAULT priv_itc_i(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_itc_i(VCPU *vcpu, INST64 inst)
{
UINT64 fault, itir, ifa, pte;
* Moves to semi-privileged registers
*************************************/
-IA64FAULT priv_mov_to_ar_imm(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_ar_imm(VCPU *vcpu, INST64 inst)
{
// I27 and M30 are identical for these fields
UINT64 ar3 = inst.M30.ar3;
return (vcpu_set_ar(vcpu,ar3,imm));
}
-IA64FAULT priv_mov_to_ar_reg(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_ar_reg(VCPU *vcpu, INST64 inst)
{
// I26 and M29 are identical for these fields
UINT64 ar3 = inst.M29.ar3;
* Moves to privileged registers
********************************/
-IA64FAULT priv_mov_to_pkr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_pkr(VCPU *vcpu, INST64 inst)
{
UINT64 r3 = vcpu_get_gr(vcpu,inst.M42.r3);
UINT64 r2 = vcpu_get_gr(vcpu,inst.M42.r2);
return (vcpu_set_pkr(vcpu,r3,r2));
}
-IA64FAULT priv_mov_to_rr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_rr(VCPU *vcpu, INST64 inst)
{
UINT64 r3 = vcpu_get_gr(vcpu,inst.M42.r3);
UINT64 r2 = vcpu_get_gr(vcpu,inst.M42.r2);
return (vcpu_set_rr(vcpu,r3,r2));
}
-IA64FAULT priv_mov_to_dbr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_dbr(VCPU *vcpu, INST64 inst)
{
UINT64 r3 = vcpu_get_gr(vcpu,inst.M42.r3);
UINT64 r2 = vcpu_get_gr(vcpu,inst.M42.r2);
return (vcpu_set_dbr(vcpu,r3,r2));
}
-IA64FAULT priv_mov_to_ibr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_ibr(VCPU *vcpu, INST64 inst)
{
UINT64 r3 = vcpu_get_gr(vcpu,inst.M42.r3);
UINT64 r2 = vcpu_get_gr(vcpu,inst.M42.r2);
return (vcpu_set_ibr(vcpu,r3,r2));
}
-IA64FAULT priv_mov_to_pmc(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_pmc(VCPU *vcpu, INST64 inst)
{
UINT64 r3 = vcpu_get_gr(vcpu,inst.M42.r3);
UINT64 r2 = vcpu_get_gr(vcpu,inst.M42.r2);
return (vcpu_set_pmc(vcpu,r3,r2));
}
-IA64FAULT priv_mov_to_pmd(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_pmd(VCPU *vcpu, INST64 inst)
{
UINT64 r3 = vcpu_get_gr(vcpu,inst.M42.r3);
UINT64 r2 = vcpu_get_gr(vcpu,inst.M42.r2);
unsigned long to_cr_cnt[128] = { 0 };
-IA64FAULT priv_mov_to_cr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_cr(VCPU *vcpu, INST64 inst)
{
UINT64 val = vcpu_get_gr(vcpu, inst.M32.r2);
to_cr_cnt[inst.M32.cr3]++;
}
}
-IA64FAULT priv_rsm(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_rsm(VCPU *vcpu, INST64 inst)
{
UINT64 imm24 = (inst.M44.i<<23)|(inst.M44.i2<<21)|inst.M44.imm;
return vcpu_reset_psr_sm(vcpu,imm24);
}
-IA64FAULT priv_ssm(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_ssm(VCPU *vcpu, INST64 inst)
{
UINT64 imm24 = (inst.M44.i<<23)|(inst.M44.i2<<21)|inst.M44.imm;
return vcpu_set_psr_sm(vcpu,imm24);
/**
* @todo Check for reserved bits and return IA64_RSVDREG_FAULT.
*/
-IA64FAULT priv_mov_to_psr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_to_psr(VCPU *vcpu, INST64 inst)
{
UINT64 val = vcpu_get_gr(vcpu, inst.M35.r2);
return vcpu_set_psr_l(vcpu,val);
* Moves from privileged registers
**********************************/
-IA64FAULT priv_mov_from_rr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_from_rr(VCPU *vcpu, INST64 inst)
{
UINT64 val;
IA64FAULT fault;
return fault;
}
-IA64FAULT priv_mov_from_pkr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_from_pkr(VCPU *vcpu, INST64 inst)
{
UINT64 val;
IA64FAULT fault;
else return fault;
}
-IA64FAULT priv_mov_from_dbr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_from_dbr(VCPU *vcpu, INST64 inst)
{
UINT64 val;
IA64FAULT fault;
else return fault;
}
-IA64FAULT priv_mov_from_ibr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_from_ibr(VCPU *vcpu, INST64 inst)
{
UINT64 val;
IA64FAULT fault;
else return fault;
}
-IA64FAULT priv_mov_from_pmc(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_from_pmc(VCPU *vcpu, INST64 inst)
{
UINT64 val;
IA64FAULT fault;
((fault = vcpu_get_##cr(vcpu,&val)) == IA64_NO_FAULT) ? \
vcpu_set_gr(vcpu, tgt, val, 0) : fault;
-IA64FAULT priv_mov_from_cr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_from_cr(VCPU *vcpu, INST64 inst)
{
UINT64 tgt = inst.M33.r1;
UINT64 val;
return IA64_ILLOP_FAULT;
}
-IA64FAULT priv_mov_from_psr(VCPU *vcpu, INST64 inst)
+static IA64FAULT priv_mov_from_psr(VCPU *vcpu, INST64 inst)
{
UINT64 tgt = inst.M33.r1;
UINT64 val;
unsigned long privop_trace = 0;
-IA64FAULT
+static IA64FAULT
priv_handle_op(VCPU *vcpu, REGS *regs, int privlvl)
{
IA64_BUNDLE bundle;