The event channel IRQ has level triggered semantics, however the current
VGIC treats everything as edge triggered.
To correctly process those IRQs, we have to lower the (virtual) IRQ line
at some point in time, depending on whether the interrupt condition
still prevails.
Check the per-VCPU evtchn_upcall_pending variable to make the interrupt
line match its status, and call this function upon every hypervisor
entry.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>
vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true);
}
+void vcpu_update_evtchn_irq(struct vcpu *v)
+{
+ bool pending = vcpu_info(v, evtchn_upcall_pending);
+
+ vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, pending);
+}
+
/* The ARM spec declares that even if local irqs are masked in
* the CPSR register, an irq should wake up a cpu from WFI anyway.
* For this reason we need to check for irqs that need delivery,
* trap and how it can be optimised.
*/
vtimer_update_irqs(current);
+ vcpu_update_evtchn_irq(current);
#endif
vgic_sync_from_lrs(current);
void vcpu_kick(struct vcpu *v);
void vcpu_mark_events_pending(struct vcpu *v);
+void vcpu_update_evtchn_irq(struct vcpu *v);
void vcpu_block_unless_event_pending(struct vcpu *v);
static inline int vcpu_event_delivery_is_enabled(struct vcpu *v)