* ARMv8 (DDI 0487A.d): D1-1509 Table D1-58
*
* Unhandled:
- * OSLSR_EL1
* DBGPRCR_EL1
*/
case HSR_SYSREG_OSLAR_EL1:
return handle_wo_wi(regs, regidx, hsr.sysreg.read, hsr, 1);
case HSR_SYSREG_OSDLR_EL1:
return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1);
+ case HSR_SYSREG_OSLSR_EL1:
+ return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 1,
+ 1 << 3);
/*
* MDCR_EL2.TDA
advance_pc(regs, hsr);
}
-/* Read only as read as zero */
-void handle_ro_raz(struct cpu_user_regs *regs,
- int regidx,
- bool read,
- const union hsr hsr,
- int min_el)
+/* Read only as value provided with 'val' argument of this function */
+void handle_ro_read_val(struct cpu_user_regs *regs,
+ int regidx,
+ bool read,
+ const union hsr hsr,
+ int min_el,
+ register_t val)
{
ASSERT((min_el == 0) || (min_el == 1));
if ( !read )
return inject_undef_exception(regs, hsr);
- /* else: raz */
- set_user_reg(regs, regidx, 0);
+ set_user_reg(regs, regidx, val);
advance_pc(regs, hsr);
}
+/* Read only as read as zero */
+inline void handle_ro_raz(struct cpu_user_regs *regs,
+ int regidx,
+ bool read,
+ const union hsr hsr,
+ int min_el)
+{
+ handle_ro_read_val(regs, regidx, read, hsr, min_el, 0);
+}
+
void dump_guest_s1_walk(struct domain *d, vaddr_t addr)
{
register_t ttbcr = READ_SYSREG(TCR_EL1);
void handle_ro_raz(struct cpu_user_regs *regs, int regidx, bool read,
const union hsr hsr, int min_el);
+/* Read only as value provided with 'val' argument */
+void handle_ro_read_val(struct cpu_user_regs *regs, int regidx, bool read,
+ const union hsr hsr, int min_el, register_t val);
+
/* Co-processor registers emulation (see arch/arm/vcpreg.c). */
void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr);
void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr);