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xen/arm: Enable CPU Erratum 1165522 for Neoverse
author
Bertrand Marquis
<bertrand.marquis@arm.com>
Tue, 18 Aug 2020 13:47:39 +0000
(14:47 +0100)
committer
Julien Grall
<jgrall@amazon.com>
Thu, 20 Aug 2020 09:19:50 +0000
(10:19 +0100)
Enable CPU erratum of Speculative AT on the Neoverse N1 processor
versions r0p0 to r2p0.
Also Fix Cortex A76 Erratum string which had a wrong errata number.
Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
Acked-by: Julien Grall <jgrall@amazon.com>
xen/arch/arm/cpuerrata.c
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diff --git
a/xen/arch/arm/cpuerrata.c
b/xen/arch/arm/cpuerrata.c
index 0248893de07225f5153e20f76fc279831fe68493..6c0901751543a05c8a7847d79c8c7f2e565c436a 100644
(file)
--- a/
xen/arch/arm/cpuerrata.c
+++ b/
xen/arch/arm/cpuerrata.c
@@
-476,9
+476,15
@@
static const struct arm_cpu_capabilities arm_errata[] = {
.matches = has_ssbd_mitigation,
},
#endif
+ {
+ /* Neoverse r0p0 - r2p0 */
+ .desc = "ARM erratum 1165522",
+ .capability = ARM64_WORKAROUND_AT_SPECULATE,
+ MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 2 << MIDR_VARIANT_SHIFT),
+ },
{
/* Cortex-A76 r0p0 - r2p0 */
- .desc = "ARM erratum 116522",
+ .desc = "ARM erratum 1165
5
22",
.capability = ARM64_WORKAROUND_AT_SPECULATE,
MIDR_RANGE(MIDR_CORTEX_A76, 0, 2 << MIDR_VARIANT_SHIFT),
},