* Errata 122 for all steppings (F+ have it disabled by default)
*/
if (c->x86 == 15) {
- rdmsrl(MSR_K7_HWCR, value);
+ rdmsrl(MSR_K8_HWCR, value);
value |= 1 << 6;
- wrmsrl(MSR_K7_HWCR, value);
+ wrmsrl(MSR_K8_HWCR, value);
}
/*
}
if (cpu_has(c, X86_FEATURE_EFRO)) {
- rdmsr(MSR_K7_HWCR, l, h);
+ rdmsr(MSR_K8_HWCR, l, h);
l |= (1 << 27); /* Enable read-only APERF/MPERF bit */
- wrmsr(MSR_K7_HWCR, l, h);
+ wrmsr(MSR_K8_HWCR, l, h);
}
/* Prevent TSC drift in non single-processor, single-core platforms. */
__set_bit(X86_FEATURE_ARAT, c->x86_capability);
if (cpu_has(c, X86_FEATURE_EFRO)) {
- rdmsrl(MSR_K7_HWCR, value);
+ rdmsrl(MSR_K8_HWCR, value);
value |= (1 << 27); /* Enable read-only APERF/MPERF bit */
- wrmsrl(MSR_K7_HWCR, value);
+ wrmsrl(MSR_K8_HWCR, value);
}
amd_log_freq(c);
#define MSR_K7_CLK_CTL 0xc001001b
#define MSR_K8_TOP_MEM2 0xc001001d
-#define MSR_K7_HWCR 0xc0010015
#define MSR_K8_HWCR 0xc0010015
#define K8_HWCR_TSC_FREQ_SEL (1ULL << 24)