x86/AMD: drop MSR_K7_HWCR
authorJan Beulich <jbeulich@suse.com>
Fri, 9 Jul 2021 06:30:35 +0000 (08:30 +0200)
committerJan Beulich <jbeulich@suse.com>
Fri, 9 Jul 2021 06:30:35 +0000 (08:30 +0200)
We don't support any K7 (32-bit only) hardware anymore, and the MSR is
accessible as MSR_K8_HWCR as well. Using the K7 name was particularly
odd for Hygon as well as in a Fam0F-specific piece of code.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/cpu/amd.c
xen/arch/x86/cpu/hygon.c
xen/include/asm-x86/msr-index.h

index 83b33047b773cf6ba872c6c6215f3808042a4a14..2260eef3aab50315fe802f01d901c6e13dc68778 100644 (file)
@@ -694,9 +694,9 @@ static void init_amd(struct cpuinfo_x86 *c)
         * Errata 122 for all steppings (F+ have it disabled by default)
         */
        if (c->x86 == 15) {
-               rdmsrl(MSR_K7_HWCR, value);
+               rdmsrl(MSR_K8_HWCR, value);
                value |= 1 << 6;
-               wrmsrl(MSR_K7_HWCR, value);
+               wrmsrl(MSR_K8_HWCR, value);
        }
 
        /*
@@ -928,9 +928,9 @@ static void init_amd(struct cpuinfo_x86 *c)
        }
 
        if (cpu_has(c, X86_FEATURE_EFRO)) {
-               rdmsr(MSR_K7_HWCR, l, h);
+               rdmsr(MSR_K8_HWCR, l, h);
                l |= (1 << 27); /* Enable read-only APERF/MPERF bit */
-               wrmsr(MSR_K7_HWCR, l, h);
+               wrmsr(MSR_K8_HWCR, l, h);
        }
 
        /* Prevent TSC drift in non single-processor, single-core platforms. */
index 2272e1113f1880e1e1a00354d27aa6bdfc060a37..67e23c5df9e3a927d53b40acc7f44a0d9f4b70ea 100644 (file)
@@ -70,9 +70,9 @@ static void init_hygon(struct cpuinfo_x86 *c)
                __set_bit(X86_FEATURE_ARAT, c->x86_capability);
 
        if (cpu_has(c, X86_FEATURE_EFRO)) {
-               rdmsrl(MSR_K7_HWCR, value);
+               rdmsrl(MSR_K8_HWCR, value);
                value |= (1 << 27); /* Enable read-only APERF/MPERF bit */
-               wrmsrl(MSR_K7_HWCR, value);
+               wrmsrl(MSR_K8_HWCR, value);
        }
 
        amd_log_freq(c);
index 7e38c257d81994c4f82ba4dc1daf7df980605c92..a14841055f0ef6ced4f3d7d2dcfceb2e1dfd39ae 100644 (file)
 #define MSR_K7_CLK_CTL                 0xc001001b
 #define MSR_K8_TOP_MEM2                        0xc001001d
 
-#define MSR_K7_HWCR                    0xc0010015
 #define MSR_K8_HWCR                    0xc0010015
 #define K8_HWCR_TSC_FREQ_SEL           (1ULL << 24)