AMD: Workaround for erratum 411

Clear APIC TMICT when we mask APIC LVTT.

Signed-off-by: Wei Wang <wei.wang2@amd.com>

diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index bd3ae1a49a54c0a4a799cc3488af4a4cf7085792..248d373667cf40dca43799fab30a354b5e98cb25 100644 (file)
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -195,6 +195,9 @@ void clear_local_APIC(void)
 
     maxlvt = get_maxlvt();
 
+    /* Work around AMD Erratum 411. This is a nice thing to do anyway. */
+    apic_write_around(APIC_TMICT, 0);
+
     /*
      * Masking an LVT entry on a P6 can trigger a local APIC error
      * if the vector is zero. Mask LVTERR first to prevent this.
@@ -1184,7 +1187,10 @@ void disable_APIC_timer(void)
 {
     if (using_apic_timer) {
         unsigned long v;
-        
+
+        /* Work around AMD Erratum 411. This is a nice thing to do anyway. */
+        apic_write_around(APIC_TMICT, 0);
+
         v = apic_read(APIC_LVTT);
         apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
     }

diff --git a/xen/arch/x86/hpet.c b/xen/arch/x86/hpet.c
index e67e5ce5d39f26f7e560bc98b42e4c02c9682700..47cc82ea210c8f2f4f694c9f5119a92597cf7eb4 100644 (file)
--- a/xen/arch/x86/hpet.c
+++ b/xen/arch/x86/hpet.c
@@ -662,8 +662,7 @@ void hpet_broadcast_enter(void)
         spin_unlock(&ch->lock);
     }
 
-    /* Cancel any outstanding LAPIC timer event and disable interrupts. */
-    reprogram_timer(0);
+    /* Disable LAPIC timer interrupts. */
     disable_APIC_timer();
 
     spin_lock(&ch->lock);