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spirv-llvm-translator-15 (15.0.0-2) unstable; urgency=medium
authorAndreas Beckmann <anbe@debian.org>
Tue, 4 Apr 2023 09:24:20 +0000 (10:24 +0100)
committerAndreas Beckmann <anbe@debian.org>
Tue, 4 Apr 2023 09:24:20 +0000 (10:24 +0100)
  * Merge changes from spirv-llvm-translator-14 14.0.0-5.
  * Restrict watch file to 15.* releases.
  * Bump Standards-Version to 4.6.2.

[dgit import unpatched spirv-llvm-translator-15 15.0.0-2]

17 files changed:
1  2 
debian/changelog patch | | | blob
debian/control patch | | | blob
debian/copyright patch | | | blob
debian/gbp.conf patch | | | blob
debian/libllvmspirvlib-15-dev.install patch | | | blob
debian/libllvmspirvlib15.install patch | | | blob
debian/libllvmspirvlib15.symbols patch | | | blob
debian/llvm-spirv-15.install patch | | | blob
debian/patches/series patch | | | blob
debian/patches/visibility-hidden.patch patch | | | blob
debian/rules patch | | | blob
debian/source/format patch | | | blob
debian/source/lintian-overrides patch | | | blob
debian/tests/control patch | | | blob
debian/tests/upstream-testsuite patch | | | blob
debian/upstream/metadata patch | | | blob
debian/watch patch | | | blob

diff --cc debian/changelog
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..8b7979307c801956989daa338a9a4fd7d4e3a63f
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/changelog
@@@ -1,0 -1,0 +1,303 @@@
++spirv-llvm-translator-15 (15.0.0-2) unstable; urgency=medium
++
++  * Merge changes from spirv-llvm-translator-14 14.0.0-5.
++  * Restrict watch file to 15.* releases.
++  * Bump Standards-Version to 4.6.2.
++
++ -- Andreas Beckmann <anbe@debian.org>  Tue, 04 Apr 2023 11:24:20 +0200
++
++spirv-llvm-translator-15 (15.0.0-1) unstable; urgency=medium
++
++  * New upstream release.
++  * Fork source package as spirv-llvm-translator-15.
++  * Rename binary packages: *14* => *15*.
++  * Build with llvm 15.
++
++ -- Andreas Beckmann <anbe@debian.org>  Mon, 03 Oct 2022 02:09:37 +0200
++
++spirv-llvm-translator-14 (14.0.0-5) unstable; urgency=medium
++
++  * Update .symbols control file.
++
++ -- Andreas Beckmann <anbe@debian.org>  Wed, 26 Oct 2022 09:11:37 +0200
++
++spirv-llvm-translator-14 (14.0.0-4) unstable; urgency=medium
++
++  * Build with -fvisibility=hidden -fvisibility-inlines-hidden.
++  * Drop hidden symbols from .symbols control file.
++
++ -- Andreas Beckmann <anbe@debian.org>  Mon, 24 Oct 2022 17:41:42 +0200
++
++spirv-llvm-translator-14 (14.0.0-3) unstable; urgency=medium
++
++  * Update .symbols control file.
++
++ -- Andreas Beckmann <anbe@debian.org>  Sun, 02 Oct 2022 13:48:53 +0200
++
++spirv-llvm-translator-14 (14.0.0-2) unstable; urgency=medium
++
++  * Restrict watch file to 14.* releases.
++  * Build with spirv-tools.
++  * Add autopkgtest, ignore failures on !amd64.
++  * Enable build-time tests, ignore failures on !amd64.
++  * Use pkg-kde-tools to manage the .symbols.
++  * Add .symbols control file.
++
++ -- Andreas Beckmann <anbe@debian.org>  Fri, 30 Sep 2022 18:00:36 +0200
++
++spirv-llvm-translator-14 (14.0.0-1) unstable; urgency=medium
++
++  * New upstream release.
++  * Fork source package as spirv-llvm-translator-14.
++  * Rename binary packages: *13* => *14*.
++  * Build with llvm 14.
++
++ -- Andreas Beckmann <anbe@debian.org>  Mon, 16 May 2022 09:29:32 +0200
++
++spirv-llvm-translator (13.0.0-6) unstable; urgency=medium
++
++  * Update .symbols control file.
++
++ -- Andreas Beckmann <anbe@debian.org>  Fri, 30 Sep 2022 16:36:05 +0200
++
++spirv-llvm-translator (13.0.0-5) unstable; urgency=medium
++
++  * Use pkg-kde-tools to manage the .symbols.
++  * Add .symbols control file.
++  * Update Lintian overrides.
++
++ -- Andreas Beckmann <anbe@debian.org>  Thu, 29 Sep 2022 22:34:44 +0200
++
++spirv-llvm-translator (13.0.0-4) unstable; urgency=medium
++
++  * Rename /usr/bin/llvm-spirv to /usr/bin/llvm-spirv-13.
++  * Restrict watch file to 13.* releases.
++  * Enable all hardening flags.
++  * Bump Standards-Version to 4.6.1.
++
++ -- Andreas Beckmann <anbe@debian.org>  Mon, 16 May 2022 01:58:34 +0200
++
++spirv-llvm-translator (13.0.0-3) unstable; urgency=medium
++
++  * Rename OpConstFunctionPointerINTEL to OpConstantFunctionPointerINTEL to
++    fix FTBFS with spirv-headers 1.5.5.  (Closes: #1005458)
++  * rules: Parse llvm version from Build-Depends.
++  * control: Provide virtual package libllvmspirvlib-13-dev.
++  * control: Set Rules-Requires-Root: no.
++  * control, install: Multiarchify the packages.
++  * upstream/metadata: Add.
++  * copyright: Update/remove outdated file patterns.
++  * Fix typo.
++  * Update Lintian overrides.
++  * Add myself to Uploaders.
++
++ -- Andreas Beckmann <anbe@debian.org>  Wed, 16 Feb 2022 23:28:24 +0100
++
++spirv-llvm-translator (13.0.0-2) unstable; urgency=medium
++
++  * control: Drop lldb-13 from build-depends, it's not used and prevents
++    build on mips/mipsel.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Wed, 17 Nov 2021 11:00:43 +0200
++
++spirv-llvm-translator (13.0.0-1) unstable; urgency=medium
++
++  * New upstream release.
++  * control: Bump debhelper to 13.
++  * control: Bump policy to 4.6.0.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Wed, 27 Oct 2021 10:41:14 +0300
++
++spirv-llvm-translator (13.0~git20210929-1) unstable; urgency=medium
++
++  * New upstream snapshot.
++  * Build with llvm 13.
++  * Add spirv-headers to build-depends, set headers dir.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Wed, 29 Sep 2021 14:40:45 +0300
++
++spirv-llvm-translator-12 (12.0.0-6) unstable; urgency=medium
++
++  * Update .symbols control file.
++
++ -- Andreas Beckmann <anbe@debian.org>  Thu, 29 Sep 2022 21:34:40 +0200
++
++spirv-llvm-translator-12 (12.0.0-5) unstable; urgency=medium
++
++  * Use pkg-kde-tools to manage the .symbols.
++  * Add .symbols control file.
++  * Update Lintian overrides.
++
++ -- Andreas Beckmann <anbe@debian.org>  Thu, 29 Sep 2022 04:13:09 +0200
++
++spirv-llvm-translator-12 (12.0.0-4) unstable; urgency=medium
++
++  * Restrict watch file to 12.* releases.
++  * Enable all hardening flags.
++  * Bump Standards-Version to 4.6.1.
++
++ -- Andreas Beckmann <anbe@debian.org>  Sun, 15 May 2022 23:58:08 +0200
++
++spirv-llvm-translator-12 (12.0.0-3) unstable; urgency=medium
++
++  [ Timo Aaltonen ]
++  * control: Bump debhelper to 13.
++  * control: Bump policy to 4.6.0.
++  * control: Drop lldb-12 from build-depends, it's not used and prevents
++    build on mips/mipsel.
++
++  [ Andreas Beckmann ]
++  * rules: Parse llvm version from Build-Depends.
++  * control: Set Rules-Requires-Root: no.
++  * control, install: Multiarchify the packages.
++  * upstream/metadata: Add.
++  * copyright: Update/remove outdated file patterns.
++  * Fix typo.
++  * Update Lintian overrides.
++  * Add myself to Uploaders.
++  * Have one set of packages per llvm version:
++    - Fork source package as spirv-llvm-translator-12.
++    - Rename binary packages:
++      + libllvmspirvlib-dev => libllvmspirvlib-12-dev,
++      + llvm-spirv => llvm-spirv-12.
++    - Rename /usr/bin/llvm-spirv to /usr/bin/llvm-spirv-12.
++
++ -- Andreas Beckmann <anbe@debian.org>  Wed, 09 Feb 2022 20:05:39 +0100
++
++spirv-llvm-translator (12.0.0-2) unstable; urgency=medium
++
++  * Upload to unstable.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Mon, 16 Aug 2021 09:59:48 +0300
++
++spirv-llvm-translator (12.0.0-1) experimental; urgency=medium
++
++  * New upstream release.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Mon, 07 Jun 2021 12:24:54 +0300
++
++spirv-llvm-translator (12.0~git20210212-2) experimental; urgency=medium
++
++  * control: Fix libllvmspirvlib-dev depends.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Mon, 10 May 2021 12:17:08 +0300
++
++spirv-llvm-translator (12.0~git20210212-1) experimental; urgency=medium
++
++  * New upstream snapshot.
++  * Build against llvm-12.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Mon, 12 Apr 2021 20:24:01 +0300
++
++spirv-llvm-translator-11 (11.0.0-4) unstable; urgency=medium
++
++  * Update .symbols control file.
++
++ -- Andreas Beckmann <anbe@debian.org>  Thu, 29 Sep 2022 03:48:48 +0200
++
++spirv-llvm-translator-11 (11.0.0-3) unstable; urgency=medium
++
++  * Use pkg-kde-tools to manage the .symbols.
++  * Add .symbols control file.
++  * Update Lintian overrides.
++
++ -- Andreas Beckmann <anbe@debian.org>  Wed, 28 Sep 2022 19:10:39 +0200
++
++spirv-llvm-translator-11 (11.0.0-2) unstable; urgency=medium
++
++  [ Timo Aaltonen ]
++  * control: Bump debhelper to 13.
++  * control: Bump policy to 4.6.0.
++  * control: Drop lldb-11 from build-depends, it's not used and prevents
++    build on mips/mipsel.
++
++  [ Andreas Beckmann ]
++  * rules: Parse llvm version from Build-Depends.
++  * control: Set Rules-Requires-Root: no.
++  * control, install: Multiarchify the packages.
++  * upstream/metadata: Add.
++  * copyright: Update/remove outdated file patterns.
++  * Fix typo.
++  * Update Lintian overrides.
++  * Add myself to Uploaders.
++  * Have one set of packages per llvm version:
++    - Fork source package as spirv-llvm-translator-11.
++    - Rename binary packages:
++      + libllvmspirvlib-dev => libllvmspirvlib-11-dev,
++      + llvm-spirv => llvm-spirv-11.
++    - Rename /usr/bin/llvm-spirv to /usr/bin/llvm-spirv-11.
++  * Allow overriding BASE_LLVM_VERSION.
++  * Restrict watch file to 11.* releases.
++  * Enable all hardening flags.
++
++ -- Andreas Beckmann <anbe@debian.org>  Mon, 11 Apr 2022 10:32:52 +0200
++
++spirv-llvm-translator (11.0.0-1) unstable; urgency=medium
++
++  * New upstream release.
++  * control: Mark -dev as M-A: same.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Tue, 20 Oct 2020 11:24:57 +0300
++
++spirv-llvm-translator (11.0~git20200922-1) unstable; urgency=medium
++
++  * New upstream snapshot.
++  * Build against llvm-11.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Tue, 22 Sep 2020 19:45:26 +0300
++
++spirv-llvm-translator (10.0.0-1) unstable; urgency=medium
++
++  * New upstream release.
++  * watch: Updated.
++  * Build against llvm-10.
++  * control: Use debhelper-compat, bump to 12.
++  * control: Bump policy to 4.5.0.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Wed, 01 Apr 2020 20:44:04 +0300
++
++spirv-llvm-translator (9.0.0-1) unstable; urgency=medium
++
++  * New upstream release.
++  * d/copyright: spirv.hpp is Expat.
++  * Build with llvm-9.
++  * patches: Dropped the only patch, applied upstream.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Tue, 24 Sep 2019 12:04:15 +0300
++
++spirv-llvm-translator (8.0.1-1) unstable; urgency=medium
++
++  * New upstream release.
++  * rules: Set build type as 'Release'.
++  * debian/patches: Refreshed.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Thu, 01 Aug 2019 10:06:44 +0300
++
++spirv-llvm-translator (8.0.0+git20190314-1) experimental; urgency=medium
++
++  * New upstream snapshot.
++  * Build a shared library.
++  * Package llvm-spirv.
++  * Add patch to support clang block syntax.
++  * rules: Drop rpath.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Wed, 20 Mar 2019 17:24:46 +0200
++
++spirv-llvm-translator (8.0.0-3) experimental; urgency=medium
++
++  * rules: Rebuild the archive index after stripping.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Fri, 15 Mar 2019 09:23:42 +0200
++
++spirv-llvm-translator (8.0.0-2) experimental; urgency=medium
++
++  * rules: Build with -fPIC.
++  * rules: Strip the library.
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Thu, 14 Mar 2019 23:53:32 +0200
++
++spirv-llvm-translator (8.0.0-1) experimental; urgency=medium
++
++  * Initial release (Closes: #921422)
++
++ -- Timo Aaltonen <tjaalton@debian.org>  Wed, 06 Feb 2019 01:40:18 +0200
diff --cc debian/control
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..56f274932d1eb185dd904d89310109e73610fb22
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/control
@@@ -1,0 -1,0 +1,71 @@@
++Source: spirv-llvm-translator-15
++Section: libdevel
++Priority: optional
++Maintainer: Debian OpenCL team <pkg-opencl-devel@lists.alioth.debian.org>
++Uploaders:
++ Timo Aaltonen <tjaalton@debian.org>,
++ Andreas Beckmann <anbe@debian.org>,
++Build-Depends: debhelper-compat (= 13),
++ dh-sequence-pkgkde-symbolshelper,
++ cmake,
++ pkgconf,
++ spirv-headers (>= 1.5.5),
++ spirv-tools,
++# keep the clang/llvm version in sync, don't forget debian/tests/control
++ libclang-15-dev,
++ llvm-15-dev,
++ clang-15 <!nocheck>,
++Rules-Requires-Root: no
++Standards-Version: 4.6.2
++Homepage: https://github.com/KhronosGroup/SPIRV-LLVM-Translator
++Vcs-Browser: https://salsa.debian.org/opencl-team/spirv-llvm-translator
++Vcs-Git: https://salsa.debian.org/opencl-team/spirv-llvm-translator.git -b llvm15/main
++
++Package: libllvmspirvlib15
++Architecture: any
++Multi-Arch: same
++Section: libs
++Depends:
++ ${shlibs:Depends},
++ ${misc:Depends}
++Description: bi-directional translator for LLVM/SPIRV -- shared library
++ SPIRV-LLVM-translator is a LLVM/SPIRV bi-directional translator. This
++ package includes a library and a tool for translation between LLVM IR
++ and SPIR-V.
++ .
++ This package includes the shared library.
++
++Package: libllvmspirvlib-15-dev
++Architecture: any
++Multi-Arch: same
++Depends:
++ libllvmspirvlib15 (= ${binary:Version}),
++ ${misc:Depends}
++Conflicts:
++ libllvmspirvlib-x.y-dev,
++Breaks:
++ libllvmspirvlib-dev (<< 13.0.0-3~),
++Replaces:
++ libllvmspirvlib-dev (<< 13.0.0-3~),
++ libllvmspirvlib-x.y-dev,
++Provides:
++ libllvmspirvlib-x.y-dev,
++Description: bi-directional translator for LLVM/SPIRV -- development files
++ SPIRV-LLVM-translator is a LLVM/SPIRV bi-directional translator. This
++ package includes a library and a tool for translation between LLVM IR
++ and SPIR-V.
++ .
++ This package includes static libs and headers for development.
++
++Package: llvm-spirv-15
++Architecture: any
++Depends:
++ libllvmspirvlib15 (= ${binary:Version}),
++ ${shlibs:Depends},
++ ${misc:Depends}
++Description: bi-directional translator for LLVM/SPIRV
++ SPIRV-LLVM-translator is a LLVM/SPIRV bi-directional translator. This
++ package includes a library and a tool for translation between LLVM IR
++ and SPIR-V.
++ .
++ This package includes the llvm-spirv-15 binary.
diff --cc debian/copyright
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..dd3ebf53103cf811b9c269fe58a4fd2ab49a62e0
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/copyright
@@@ -1,0 -1,0 +1,70 @@@
++Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
++Upstream-Name: spirv-llvm-translator
++Source: https://github.com/KhronosGroup/SPIRV-LLVM-Translator
++
++Files: *
++Copyright: 2014 Advanced Micro Devices, Inc.
++           2018-2021 Intel Corporation
++License: BSD-3-clause
++
++Files:
++ lib/SPIRV/libSPIRV/OpenCL.std.h
++ lib/SPIRV/libSPIRV/spirv_internal.hpp
++Copyright: 2015-2020 The Khronos Group Inc.
++License: Expat
++
++Files: debian/*
++Copyright: 2019 Timo Aaltonen <tjaalton@debian.org>
++           © 2022 Andreas Beckmann <anbe@debian.org>
++License: BSD-3-clause
++
++License: BSD-3-clause
++ Permission is hereby granted, free of charge, to any person obtaining a copy of
++ this software and associated documentation files (the "Software"), to deal with
++ the Software without restriction, including without limitation the rights to
++ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ of the Software, and to permit persons to whom the Software is furnished to do
++ so, subject to the following conditions:
++ .
++    * Redistributions of source code must retain the above copyright notice,
++      this list of conditions and the following disclaimers.
++ .
++    * Redistributions in binary form must reproduce the above copyright notice,
++      this list of conditions and the following disclaimers in the
++      documentation and/or other materials provided with the distribution.
++ .
++    * Neither the names of the LLVM Team, University of Illinois at
++      Urbana-Champaign, nor the names of its contributors may be used to
++      endorse or promote products derived from this Software without specific
++      prior written permission.
++ .
++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
++ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
++ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
++ SOFTWARE.
++
++License: Expat
++ Permission is hereby granted, free of charge, to any person obtaining a copy
++ of this software and/or associated documentation files (the "Materials"),
++ to deal in the Materials without restriction, including without limitation
++ the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ and/or sell copies of the Materials, and to permit persons to whom the
++ Materials are furnished to do so, subject to the following conditions:
++ .
++ The above copyright notice and this permission notice shall be included in
++ all copies or substantial portions of the Materials.
++ .
++ MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS KHRONOS
++ STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS SPECIFICATIONS AND
++ HEADER INFORMATION ARE LOCATED AT https://www.khronos.org/registry/
++ .
++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ FROM,OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER DEALINGS
++ IN THE MATERIALS.
diff --cc debian/gbp.conf
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..c543182685f684dae1679dddbad21592fc3c4313
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/gbp.conf
@@@ -1,0 -1,0 +1,3 @@@
++[DEFAULT]
++upstream-vcs-tag = v%(version)s
++debian-branch = llvm15/main
diff --cc debian/libllvmspirvlib-15-dev.install
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..82bf11155a1457ce8c4d08bc1d07bf8c400123fd
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/libllvmspirvlib-15-dev.install
@@@ -1,0 -1,0 +1,3 @@@
++usr/include
++usr/lib/libLLVMSPIRVLib.so            usr/lib/${DEB_HOST_MULTIARCH}/
++usr/lib/pkgconfig/LLVMSPIRVLib.pc     usr/lib/${DEB_HOST_MULTIARCH}/pkgconfig/
diff --cc debian/libllvmspirvlib15.install
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..6fb00dfb81edb69848095d52190f0125826f39c6
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/libllvmspirvlib15.install
@@@ -1,0 -1,0 +1,1 @@@
++usr/lib/libLLVMSPIRVLib.so.*  usr/lib/${DEB_HOST_MULTIARCH}/
diff --cc debian/libllvmspirvlib15.symbols
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..df8965297440812372d247ebe36f93f7e67a5076
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/libllvmspirvlib15.symbols
@@@ -1,0 -1,0 +1,477 @@@
++# SymbolsHelper-Confirmed: 15 amd64 arm64 armel i386 powerpc ppc64 ppc64el s390x sparc64 x32
++libLLVMSPIRVLib.so.15 #PACKAGE# #MINVER#
++* Build-Depends-Package: libllvmspirvlib-15-dev
++ _ZGVZNKSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0ELb0EEclEcE5__nul@Base 0
++ _ZGVZNKSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0ELb1EEclEcE5__nul@Base 0
++ _ZGVZNKSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1ELb0EEclEcE5__nul@Base 0
++ _ZGVZNKSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1ELb1EEclEcE5__nul@Base 0
++ _ZN4llvm10writeSpirvEPNS_6ModuleERKN5SPIRV14TranslatorOptsERSoRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@Base 0
++ _ZN4llvm10writeSpirvEPNS_6ModuleERSoRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@Base 0
++ _ZN4llvm16getSpecConstInfoERSiRSt6vectorISt4pairIjjESaIS3_EE@Base 0
++ _ZN4llvm18convertSpirvToLLVMERNS_11LLVMContextERN5SPIRV11SPIRVModuleERKNS2_14TranslatorOptsERNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@Base 0
++ _ZN4llvm18convertSpirvToLLVMERNS_11LLVMContextERN5SPIRV11SPIRVModuleERNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@Base 0
++ _ZN4llvm19mangleOpenClBuiltinERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEENS_8ArrayRefIPNS_4TypeEEENS8_INS_14PointerIntPairISA_Lj1EbNS_21PointerLikeTypeTraitsISA_EENS_18PointerIntPairInfoISA_Lj1ESE_EEEEEERS5_@Base 15
++ _ZN4llvm21createSPIRVWriterPassERSo@Base 0
++ _ZN4llvm21createSPIRVWriterPassERSoRKN5SPIRV14TranslatorOptsE@Base 0
++ _ZN4llvm22createOCLToSPIRVLegacyEv@Base 13
++ _ZN4llvm22regularizeLlvmForSpirvEPNS_6ModuleERNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@Base 0
++ _ZN4llvm22regularizeLlvmForSpirvEPNS_6ModuleERNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKN5SPIRV14TranslatorOptsE@Base 0
++ _ZN4llvm23createLLVMToSPIRVLegacyEPN5SPIRV11SPIRVModuleE@Base 13
++ _ZN4llvm24createSPIRVToOCL12LegacyEv@Base 13
++ _ZN4llvm24createSPIRVToOCL20LegacyEv@Base 13
++ _ZN4llvm26createOCLTypeToSPIRVLegacyEv@Base 13
++ _ZN4llvm26createSPIRVBIsLoweringPassERNS_6ModuleEN5SPIRV17BIsRepresentationE@Base 0
++ _ZN4llvm26createSPIRVLowerBoolLegacyEv@Base 13
++ _ZN4llvm29createSPIRVLowerMemmoveLegacyEv@Base 13
++ _ZN4llvm30createPreprocessMetadataLegacyEv@Base 13
++ _ZN4llvm30initializeOCLToSPIRVLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm31createSPIRVLowerConstExprLegacyEv@Base 13
++ _ZN4llvm31createSPIRVLowerOCLBlocksLegacyEv@Base 13
++ _ZN4llvm31createSPIRVRegularizeLLVMLegacyEv@Base 13
++ _ZN4llvm31initializeLLVMToSPIRVLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm32initializeSPIRVToOCL12LegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm32initializeSPIRVToOCL20LegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm34initializeOCLTypeToSPIRVLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm34initializeSPIRVLowerBoolLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm36createSPIRVLowerSaddIntrinsicsLegacyEv@Base 15
++ _ZN4llvm37initializeSPIRVLowerMemmoveLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm38initializePreprocessMetadataLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm39initializeSPIRVLowerConstExprLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm39initializeSPIRVLowerOCLBlocksLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm39initializeSPIRVRegularizeLLVMLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm44initializeSPIRVLowerSaddIntrinsicsLegacyPassERNS_12PassRegistryE@Base 15
++ _ZN4llvm46createSPIRVLowerBitCastToNonStandardTypeLegacyERKN5SPIRV14TranslatorOptsE@Base 14
++ _ZN4llvm54initializeSPIRVLowerBitCastToNonStandardTypeLegacyPassERNS_12PassRegistryE@Base 13
++ _ZN4llvm9readSpirvERNS_11LLVMContextERKN5SPIRV14TranslatorOptsERSiRPNS_6ModuleERNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@Base 0
++ _ZN4llvm9readSpirvERNS_11LLVMContextERSiRPNS_6ModuleERNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@Base 0
++ _ZN5SPIRV12convertSpirvERNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES6_S6_b@Base 0
++ _ZN5SPIRV12convertSpirvERSiRSoRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEbb@Base 0
++ _ZN5SPIRV14TranslatorOpts30setSPIRVAllowUnknownIntrinsicsEN4llvm11SmallVectorINS1_9StringRefELj4EEE@Base 13
++ _ZN5SPIRV15readSpirvModuleERSiRKNS_14TranslatorOptsERNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@Base 0
++ _ZN5SPIRV15readSpirvModuleERSiRNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@Base 0
++ _ZN5SPIRV18SPIRVUseTextFormatE@Base 0
++ _ZNK5SPIRV14TranslatorOpts25isUnknownIntrinsicAllowedEPN4llvm13IntrinsicInstE@Base 13
++ _ZNK5SPIRV14TranslatorOpts36isSPIRVAllowUnknownIntrinsicsEnabledEv@Base 13
++ (optional=templinst)_ZNKSt10_HashtableIjjSaIjENSt8__detail9_IdentityESt8equal_toIjESt4hashIjENS1_18_Mod_range_hashingENS1_20_Default_ranged_hashENS1_20_Prime_rehash_policyENS1_17_Hashtable_traitsILb0ELb1ELb1EEEE4findERKj@Base 14
++ (optional=templinst)_ZNKSt7__cxx1112regex_traitsIcE16lookup_classnameIPKcEENS1_10_RegexMaskET_S6_b@Base 0
++ (optional=templinst)_ZNKSt7__cxx1112regex_traitsIcE18lookup_collatenameIPKcEENS_12basic_stringIcSt11char_traitsIcESaIcEEET_SA_@Base 0
++ (optional=templinst)_ZNKSt7__cxx1114regex_iteratorIPKccNS_12regex_traitsIcEEEeqERKS5_@Base 14
++ (optional=templinst)_ZNKSt8_Rb_treeIN3spv2OpESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE4findERS3_@Base 14
++ (optional=templinst)_ZNKSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv2OpEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE4findERS7_@Base 0
++ (optional=templinst)_ZNKSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb0EE16_M_word_boundaryEv@Base 0
++ (optional=templinst)_ZNKSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb1EE16_M_word_boundaryEv@Base 0
++ (optional=templinst|subst)_ZNSt10_HashtableIPKN4llvm8FunctionES3_SaIS3_ENSt8__detail9_IdentityESt8equal_toIS3_ESt4hashIS3_ENS5_18_Mod_range_hashingENS5_20_Default_ranged_hashENS5_20_Prime_rehash_policyENS5_17_Hashtable_traitsILb0ELb1ELb1EEEE21_M_insert_unique_nodeE{size_t}{size_t}PNS5_10_Hash_nodeIS3_Lb0EEE{size_t}@Base 0
++ (optional=templinst|subst)_ZNSt10_HashtableIjSt4pairIKj{uint64_t}ESaIS2_ENSt8__detail10_Select1stESt8equal_toIjESt4hashIjENS4_18_Mod_range_hashingENS4_20_Default_ranged_hashENS4_20_Prime_rehash_policyENS4_17_Hashtable_traitsILb0ELb0ELb1EEEE18_M_assign_elementsIRKSF_EEvOT_@Base 0
++ (optional=templinst|subst|arch=!armel !armhf !mipsel !powerpc)_ZNSt10_HashtableIjSt4pairIKj{uint64_t}ESaIS2_ENSt8__detail10_Select1stESt8equal_toIjESt4hashIjENS4_18_Mod_range_hashingENS4_20_Default_ranged_hashENS4_20_Prime_rehash_policyENS4_17_Hashtable_traitsILb0ELb0ELb1EEEE9_M_assignIRKSF_NS4_17_ReuseOrAllocNodeISaINS4_10_Hash_nodeIS2_Lb0EEEEEEEEvOT_RKT0_@Base 0
++ (optional=templinst|arch=mips64el mipsel riscv64 sparc64 x32|subst)_ZNSt11_Deque_baseIlSaIlEE17_M_initialize_mapE{size_t}@Base 0
++ (optional=templinst)_ZNSt11_Deque_baseIlSaIlEED1Ev@Base 0
++ (optional=templinst)_ZNSt11_Deque_baseIlSaIlEED2Ev@Base 0
++ (optional=templinst|subst|arch=!ppc64 !s390x)_ZNSt17_Temporary_bufferIN9__gnu_cxx17__normal_iteratorIPSt4pairIjjESt6vectorIS3_SaIS3_EEEES3_EC1ES8_{ssize_t}@Base 13
++ (optional=templinst|subst|arch=!ppc64 !s390x)_ZNSt17_Temporary_bufferIN9__gnu_cxx17__normal_iteratorIPSt4pairIjjESt6vectorIS3_SaIS3_EEEES3_EC2ES8_{ssize_t}@Base 13
++ (optional=templinst)_ZNSt5dequeINSt8__detail9_StateSeqINSt7__cxx1112regex_traitsIcEEEESaIS5_EE12emplace_backIJS5_EEEvDpOT_@Base 0
++ (optional=templinst)_ZNSt5dequeINSt8__detail9_StateSeqINSt7__cxx1112regex_traitsIcEEEESaIS5_EE16_M_push_back_auxIJRKS5_EEEvDpOT_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !x32)_ZNSt5dequeINSt8__detail9_StateSeqINSt7__cxx1112regex_traitsIcEEEESaIS5_EE16_M_push_back_auxIJS5_EEEvDpOT_@Base 0
++ (optional=templinst|subst)_ZNSt5dequeINSt8__detail9_StateSeqINSt7__cxx1112regex_traitsIcEEEESaIS5_EE17_M_reallocate_mapE{size_t}b@Base 0
++ (optional=templinst)_ZNSt5dequeIlSaIlEE16_M_push_back_auxIJRKlEEEvDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorIN3spv10CapabilityESaIS1_EE12emplace_backIJS1_EEEvDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorIN3spv10CapabilityESaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_@Base 0
++ (optional=templinst|subst)_ZNSt6vectorIN3spv15AccessQualifierESaIS1_EE17_M_default_appendE{size_t}@Base 0
++ (optional=templinst)_ZNSt6vectorIN3spv15AccessQualifierESaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_@Base 15
++ (optional=templinst)_ZNSt6vectorINSt7__cxx1112regex_traitsIcE10_RegexMaskESaIS3_EE17_M_realloc_insertIJRKS3_EEEvN9__gnu_cxx17__normal_iteratorIPS3_S5_EEDpOT_@Base 0
++ (optional=templinst|subst)_ZNSt6vectorINSt7__cxx119sub_matchIPKcEESaIS4_EE14_M_fill_assignE{size_t}RKS4_@Base 0
++ (optional=templinst)_ZNSt6vectorINSt8__detail6_StateIcEESaIS2_EE17_M_realloc_insertIJS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorIPN4llvm8FunctionESaIS2_EE17_M_realloc_insertIJS2_EEEvN9__gnu_cxx17__normal_iteratorIPS2_S4_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorISt4pairIN3spv10DecorationES_INSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS8_EEESaISB_EE12emplace_backIJS2_SA_EEEvDpOT_@Base 15
++ (optional=templinst)_ZNSt6vectorISt4pairIN3spv10DecorationES_INSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS8_EEESaISB_EE17_M_realloc_insertIJRS2_SA_EEEvN9__gnu_cxx17__normal_iteratorIPSB_SD_EEDpOT_@Base 15
++ (optional=templinst)_ZNSt6vectorISt4pairIN3spv10DecorationES_INSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS8_EEESaISB_EE17_M_realloc_insertIJS2_SA_EEEvN9__gnu_cxx17__normal_iteratorIPSB_SD_EEDpOT_@Base 15
++ (optional=templinst)_ZNSt6vectorISt4pairINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES6_ESaIS7_EE17_M_realloc_insertIJS7_EEEvN9__gnu_cxx17__normal_iteratorIPS7_S9_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorISt4pairIccESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorISt4pairIjjESaIS1_EE12emplace_backIJN3spv15LoopControlMaskERjEEEvDpOT_@Base 12
++ (optional=templinst|arch=!armel !armhf !hurd-i386 !i386 !mipsel !powerpc !x32)_ZNSt6vectorISt4pairIjjESaIS1_EE12emplace_backIJN3spv15LoopControlMaskERmEEEvDpOT_@Base 12
++ (optional=templinst)_ZNSt6vectorISt4pairIjjESaIS1_EE12emplace_backIJN3spv15LoopControlMaskEiEEEvDpOT_@Base 12
++ (optional=templinst|arch=armel armhf hurd-i386 i386 mipsel powerpc x32)_ZNSt6vectorISt4pairIjjESaIS1_EE12emplace_backIJN3spv15LoopControlMaskEjEEEvDpOT_@Base 12
++ (optional=templinst|arch=!armel !armhf !hurd-i386 !i386 !mipsel !powerpc !x32)_ZNSt6vectorISt4pairIjjESaIS1_EE12emplace_backIJN3spv15LoopControlMaskEmEEEvDpOT_@Base 12
++ (optional=templinst)_ZNSt6vectorISt4pairIjjESaIS1_EE12emplace_backIJRKN3spv15LoopControlMaskEjEEEvDpOT_@Base 13
++ (optional=templinst)_ZNSt6vectorISt4pairIjjESaIS1_EE12emplace_backIJRKjRjEEEvDpOT_@Base 0
++ (optional=templinst|arch=armel armhf hurd-i386 i386 mipsel powerpc)_ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJRjS5_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_@Base 0
++ (optional=templinst|arch=!x32)_ZNSt6vectorISt4pairIlS_INSt7__cxx119sub_matchIPKcEESaIS5_EEESaIS8_EE12emplace_backIJRlRKS7_EEEvDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorISt4pairIlS_INSt7__cxx119sub_matchIPKcEESaIS5_EEESaIS8_EE17_M_realloc_insertIJRlRKS7_EEEvN9__gnu_cxx17__normal_iteratorIPS8_SA_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorIcSaIcEE12emplace_backIJcEEEvDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorIcSaIcEE17_M_realloc_insertIJcEEEvN9__gnu_cxx17__normal_iteratorIPcS1_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorIiSaIiEE12emplace_backIJiEEEvDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorIjSaIjEE12emplace_backIJjEEEvDpOT_@Base 0
++ (optional=templinst|arch=armel armhf hurd-i386 i386 mipsel powerpc x32)_ZNSt6vectorIjSaIjEE14_M_fill_insertEN9__gnu_cxx17__normal_iteratorIPjS1_EEjRKj@Base 12
++ (optional=templinst|arch=!armel !armhf !hurd-i386 !i386 !mipsel !powerpc !x32)_ZNSt6vectorIjSaIjEE14_M_fill_insertEN9__gnu_cxx17__normal_iteratorIPjS1_EEmRKj@Base 12
++ (optional=templinst|subst)_ZNSt6vectorIjSaIjEE17_M_default_appendE{size_t}@Base 0
++ (optional=templinst)_ZNSt6vectorIjSaIjEE17_M_realloc_insertIJRKjEEEvN9__gnu_cxx17__normal_iteratorIPjS1_EEDpOT_@Base 0
++ (optional=templinst)_ZNSt6vectorIjSaIjEE17_M_realloc_insertIJjEEEvN9__gnu_cxx17__normal_iteratorIPjS1_EEDpOT_@Base 0
++ (optional=templinst|arch=!armel !armhf !hurd-i386 !i386 !mipsel !powerpc !x32)_ZNSt6vectorImSaImEE17_M_realloc_insertIJRKmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_@Base 0
++ (optional=templinst|subst)_ZNSt6vectorI{uint64_t}SaI{uint64_t}EE17_M_realloc_insertIJ{uint64_t}EEEvN9__gnu_cxx17__normal_iteratorIP{uint64_t}S1_EEDpOT_@Base 14
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeI14VCFloatControlSt4pairIKS0_N17VectorComputeUtil11VCFloatTypeEESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS2_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeI14VCFloatControlSt4pairIKS0_N17VectorComputeUtil11VCFloatTypeEESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE24_M_get_insert_unique_posERS2_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeI14VCFloatControlSt4pairIKS0_N17VectorComputeUtil11VCFloatTypeEESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS2_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeI14VCFloatControlSt4pairIKS0_N3spv14FPRoundingModeEESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS2_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeI14VCFloatControlSt4pairIKS0_N3spv14FPRoundingModeEESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE24_M_get_insert_unique_posERS2_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeI14VCFloatControlSt4pairIKS0_N3spv14FPRoundingModeEESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS2_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeI14VCFloatControlSt4pairIKS0_N3spv15FPOperationModeEESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS2_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeI14VCFloatControlSt4pairIKS0_N3spv15FPOperationModeEESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE24_M_get_insert_unique_posERS2_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeI14VCFloatControlSt4pairIKS0_N3spv15FPOperationModeEESt10_Select1stIS5_ESt4lessIS0_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS2_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN10SPIRVDebug11EncodingTagESt4pairIKS1_N4llvm5dwarf8TypeKindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN10SPIRVDebug11EncodingTagESt4pairIKS1_N4llvm5dwarf8TypeKindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN10SPIRVDebug11EncodingTagESt4pairIKS1_N4llvm5dwarf8TypeKindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN10SPIRVDebug11InstructionESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN10SPIRVDebug11InstructionESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN10SPIRVDebug16CompositeTypeTagESt4pairIKS1_N4llvm5dwarf3TagEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN10SPIRVDebug16CompositeTypeTagESt4pairIKS1_N4llvm5dwarf3TagEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN10SPIRVDebug16CompositeTypeTagESt4pairIKS1_N4llvm5dwarf3TagEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN10SPIRVDebug16ExpressionOpCodeESt4pairIKS1_N4llvm5dwarf12LocationAtomEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN10SPIRVDebug16ExpressionOpCodeESt4pairIKS1_N4llvm5dwarf12LocationAtomEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN10SPIRVDebug16ExpressionOpCodeESt4pairIKS1_N4llvm5dwarf12LocationAtomEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN10SPIRVDebug16ExpressionOpCodeESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN10SPIRVDebug16ExpressionOpCodeESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN10SPIRVDebug16TypeQualifierTagESt4pairIKS1_N4llvm5dwarf3TagEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN10SPIRVDebug16TypeQualifierTagESt4pairIKS1_N4llvm5dwarf3TagEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN10SPIRVDebug16TypeQualifierTagESt4pairIKS1_N4llvm5dwarf3TagEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN10SPIRVDebug17ImportedEntityTagESt4pairIKS1_N4llvm5dwarf3TagEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN10SPIRVDebug17ImportedEntityTagESt4pairIKS1_N4llvm5dwarf3TagEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN10SPIRVDebug17ImportedEntityTagESt4pairIKS1_N4llvm5dwarf3TagEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN17VectorComputeUtil11VCFloatTypeESt4pairIKS1_14VCFloatControlESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN17VectorComputeUtil11VCFloatTypeESt4pairIKS1_14VCFloatControlESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN17VectorComputeUtil11VCFloatTypeESt4pairIKS1_14VCFloatControlESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN17VectorComputeUtil11VCFloatTypeESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESF_IJEEEEESt17_Rb_tree_iteratorIS4_ESt23_Rb_tree_const_iteratorIS4_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN17VectorComputeUtil11VCFloatTypeESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN17VectorComputeUtil11VCFloatTypeESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv10CapabilityESt4pairIKS1_N7OCLUtil6OclExt4KindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv10CapabilityESt4pairIKS1_N7OCLUtil6OclExt4KindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv10CapabilityESt4pairIKS1_N7OCLUtil6OclExt4KindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv10CapabilityESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv10CapabilityESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv10CapabilityESt4pairIKS1_St6vectorIS1_SaIS1_EEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv10CapabilityESt4pairIKS1_St6vectorIS1_SaIS1_EEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv10DecorationESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv10DecorationESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv10DecorationESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv10DecorationESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv11LinkageTypeESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv11LinkageTypeESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv12FPDenormModeESt4pairIKS1_NS0_13ExecutionModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv12FPDenormModeESt4pairIKS1_NS0_13ExecutionModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv12FPDenormModeESt4pairIKS1_NS0_13ExecutionModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv12StorageClassESt4pairIKS1_N5SPIRV16SPIRAddressSpaceEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESH_IJEEEEESt17_Rb_tree_iteratorIS6_ESt23_Rb_tree_const_iteratorIS6_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv12StorageClassESt4pairIKS1_N5SPIRV16SPIRAddressSpaceEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv12StorageClassESt4pairIKS1_N5SPIRV16SPIRAddressSpaceEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS6_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv12StorageClassESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv12StorageClassESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_NS0_12FPDenormModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_NS0_12FPDenormModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_NS0_12FPDenormModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_NS0_14FPRoundingModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_NS0_14FPRoundingModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_NS0_14FPRoundingModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_NS0_15FPOperationModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_NS0_15FPOperationModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_NS0_15FPOperationModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv13ExecutionModeESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv14ExecutionModelESt4pairIKS1_St3setIjSt4lessIjESaIjEEESt10_Select1stIS9_ES5_IS1_ESaIS9_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv14ExecutionModelESt4pairIKS1_St3setIjSt4lessIjESaIjEEESt10_Select1stIS9_ES5_IS1_ESaIS9_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS9_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv14ExecutionModelESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv14ExecutionModelESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv14FPRoundingModeESt4pairIKS1_14VCFloatControlESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv14FPRoundingModeESt4pairIKS1_14VCFloatControlESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv14FPRoundingModeESt4pairIKS1_14VCFloatControlESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv14FPRoundingModeESt4pairIKS1_NS0_13ExecutionModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv14FPRoundingModeESt4pairIKS1_NS0_13ExecutionModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv14FPRoundingModeESt4pairIKS1_NS0_13ExecutionModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv14FPRoundingModeESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv14FPRoundingModeESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv14GroupOperationESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv14GroupOperationESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv15AccessQualifierESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv15AccessQualifierESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv15FPOperationModeESt4pairIKS1_14VCFloatControlESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv15FPOperationModeESt4pairIKS1_14VCFloatControlESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv15FPOperationModeESt4pairIKS1_14VCFloatControlESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv15FPOperationModeESt4pairIKS1_NS0_13ExecutionModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESG_IJEEEEESt17_Rb_tree_iteratorIS5_ESt23_Rb_tree_const_iteratorIS5_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv15FPOperationModeESt4pairIKS1_NS0_13ExecutionModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv15FPOperationModeESt4pairIKS1_NS0_13ExecutionModeEESt10_Select1stIS5_ESt4lessIS1_ESaIS5_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS5_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv19FunctionControlMaskESt4pairIKS1_N4llvm9Attribute8AttrKindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv19FunctionControlMaskESt4pairIKS1_N4llvm9Attribute8AttrKindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv19FunctionControlMaskESt4pairIKS1_N4llvm9Attribute8AttrKindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv19MemorySemanticsMaskESt4pairIKS1_N7OCLUtil15OCLMemFenceKindEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESH_IJEEEEESt17_Rb_tree_iteratorIS6_ESt23_Rb_tree_const_iteratorIS6_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv19MemorySemanticsMaskESt4pairIKS1_N7OCLUtil15OCLMemFenceKindEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv19MemorySemanticsMaskESt4pairIKS1_N7OCLUtil15OCLMemFenceKindEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS6_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv19MemorySemanticsMaskESt4pairIKS1_N7OCLUtil23OCLMemFenceExtendedKindEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESH_IJEEEEESt17_Rb_tree_iteratorIS6_ESt23_Rb_tree_const_iteratorIS6_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv19MemorySemanticsMaskESt4pairIKS1_N7OCLUtil23OCLMemFenceExtendedKindEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv19MemorySemanticsMaskESt4pairIKS1_N7OCLUtil23OCLMemFenceExtendedKindEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS6_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv26FunctionParameterAttributeESt4pairIKS1_N4llvm9Attribute8AttrKindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv26FunctionParameterAttributeESt4pairIKS1_N4llvm9Attribute8AttrKindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv26FunctionParameterAttributeESt4pairIKS1_N4llvm9Attribute8AttrKindEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_N4llvm13AtomicRMWInst5BinOpEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_N4llvm13AtomicRMWInst5BinOpEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_N4llvm13AtomicRMWInst5BinOpEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_N4llvm7CmpInst9PredicateEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_N4llvm7CmpInst9PredicateEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_N4llvm7CmpInst9PredicateEESt10_Select1stIS7_ESt4lessIS1_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_S1_ESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESF_IJEEEEESt17_Rb_tree_iteratorIS4_ESt23_Rb_tree_const_iteratorIS4_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_S1_ESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_S1_ESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESF_IJEEEEESt17_Rb_tree_iteratorIS4_ESt23_Rb_tree_const_iteratorIS4_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv2OpESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN3spv5ScopeESt4pairIKS1_N7OCLUtil12OCLScopeKindEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESH_IJEEEEESt17_Rb_tree_iteratorIS6_ESt23_Rb_tree_const_iteratorIS6_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv5ScopeESt4pairIKS1_N7OCLUtil12OCLScopeKindEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv5ScopeESt4pairIKS1_N7OCLUtil12OCLScopeKindEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS6_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv5ScopeESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 14
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv5ScopeESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 14
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv7BuiltInESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv7BuiltInESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv7BuiltInESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE24_M_get_insert_unique_posERS3_@Base 12
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv7BuiltInESt4pairIKS1_St6vectorINS0_10CapabilityESaIS5_EEESt10_Select1stIS8_ESt4lessIS1_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS3_@Base 12
++ (optional=templinst)_ZNSt8_Rb_treeIN3spv8internal25InternalJointMatrixLayoutESt4pairIKS2_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISB_ESt4lessIS2_ESaISB_EE24_M_get_insert_unique_posERS4_@Base 14
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN3spv8internal25InternalJointMatrixLayoutESt4pairIKS2_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISB_ESt4lessIS2_ESaISB_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISB_ERS4_@Base 14
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN4llvm13AtomicRMWInst5BinOpESt4pairIKS2_N3spv2OpEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN4llvm13AtomicRMWInst5BinOpESt4pairIKS2_N3spv2OpEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN4llvm13AtomicRMWInst5BinOpESt4pairIKS2_N3spv2OpEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN4llvm5dwarf12LocationAtomESt4pairIKS2_N10SPIRVDebug16ExpressionOpCodeEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN4llvm5dwarf12LocationAtomESt4pairIKS2_N10SPIRVDebug16ExpressionOpCodeEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN4llvm5dwarf12LocationAtomESt4pairIKS2_N10SPIRVDebug16ExpressionOpCodeEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN4llvm5dwarf3TagESt4pairIKS2_N10SPIRVDebug16CompositeTypeTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN4llvm5dwarf3TagESt4pairIKS2_N10SPIRVDebug16CompositeTypeTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN4llvm5dwarf3TagESt4pairIKS2_N10SPIRVDebug16CompositeTypeTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN4llvm5dwarf3TagESt4pairIKS2_N10SPIRVDebug16TypeQualifierTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN4llvm5dwarf3TagESt4pairIKS2_N10SPIRVDebug16TypeQualifierTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN4llvm5dwarf3TagESt4pairIKS2_N10SPIRVDebug16TypeQualifierTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN4llvm5dwarf3TagESt4pairIKS2_N10SPIRVDebug17ImportedEntityTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN4llvm5dwarf3TagESt4pairIKS2_N10SPIRVDebug17ImportedEntityTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN4llvm5dwarf3TagESt4pairIKS2_N10SPIRVDebug17ImportedEntityTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN4llvm5dwarf8TypeKindESt4pairIKS2_N10SPIRVDebug11EncodingTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN4llvm5dwarf8TypeKindESt4pairIKS2_N10SPIRVDebug11EncodingTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN4llvm5dwarf8TypeKindESt4pairIKS2_N10SPIRVDebug11EncodingTagEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN4llvm7CmpInst9PredicateESt4pairIKS2_N3spv2OpEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN4llvm7CmpInst9PredicateESt4pairIKS2_N3spv2OpEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN4llvm7CmpInst9PredicateESt4pairIKS2_N3spv2OpEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN4llvm9Attribute8AttrKindESt4pairIKS2_N3spv19FunctionControlMaskEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN4llvm9Attribute8AttrKindESt4pairIKS2_N3spv19FunctionControlMaskEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN4llvm9Attribute8AttrKindESt4pairIKS2_N3spv19FunctionControlMaskEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN4llvm9Attribute8AttrKindESt4pairIKS2_N3spv26FunctionParameterAttributeEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN4llvm9Attribute8AttrKindESt4pairIKS2_N3spv26FunctionParameterAttributeEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN4llvm9Attribute8AttrKindESt4pairIKS2_N3spv26FunctionParameterAttributeEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN5SPIRV11ExtensionIDESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN5SPIRV11ExtensionIDESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN5SPIRV11ExtensionIDESt4pairIKS1_bESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJOS1_EESF_IJEEEEESt17_Rb_tree_iteratorIS4_ESt23_Rb_tree_const_iteratorIS4_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN5SPIRV11ExtensionIDESt4pairIKS1_bESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN5SPIRV11ExtensionIDESt4pairIKS1_bESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN5SPIRV14SPIRVErrorCodeESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN5SPIRV14SPIRVErrorCodeESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN5SPIRV16SPIRAddressSpaceESt4pairIKS1_N3spv12StorageClassEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESH_IJEEEEESt17_Rb_tree_iteratorIS6_ESt23_Rb_tree_const_iteratorIS6_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN5SPIRV16SPIRAddressSpaceESt4pairIKS1_N3spv12StorageClassEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN5SPIRV16SPIRAddressSpaceESt4pairIKS1_N3spv12StorageClassEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS6_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN5SPIRV19SPIRVExtInstSetKindESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN5SPIRV19SPIRVExtInstSetKindESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN5SPIRV19SPIRVExtInstSetKindESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN5SPIRV19SPIRVExtInstSetKindESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN7OCLUtil12OCLScopeKindESt4pairIKS1_N3spv5ScopeEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESH_IJEEEEESt17_Rb_tree_iteratorIS6_ESt23_Rb_tree_const_iteratorIS6_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN7OCLUtil12OCLScopeKindESt4pairIKS1_N3spv5ScopeEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN7OCLUtil12OCLScopeKindESt4pairIKS1_N3spv5ScopeEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS6_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN7OCLUtil15OCLMemFenceKindESt4pairIKS1_N3spv19MemorySemanticsMaskEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESH_IJEEEEESt17_Rb_tree_iteratorIS6_ESt23_Rb_tree_const_iteratorIS6_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN7OCLUtil15OCLMemFenceKindESt4pairIKS1_N3spv19MemorySemanticsMaskEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN7OCLUtil15OCLMemFenceKindESt4pairIKS1_N3spv19MemorySemanticsMaskEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS6_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN7OCLUtil15OCLMemOrderKindESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESF_IJEEEEESt17_Rb_tree_iteratorIS4_ESt23_Rb_tree_const_iteratorIS4_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN7OCLUtil15OCLMemOrderKindESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN7OCLUtil15OCLMemOrderKindESt4pairIKS1_jESt10_Select1stIS4_ESt4lessIS1_ESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS3_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN7OCLUtil23OCLMemFenceExtendedKindESt4pairIKS1_N3spv19MemorySemanticsMaskEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS3_EESH_IJEEEEESt17_Rb_tree_iteratorIS6_ESt23_Rb_tree_const_iteratorIS6_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN7OCLUtil23OCLMemFenceExtendedKindESt4pairIKS1_N3spv19MemorySemanticsMaskEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN7OCLUtil23OCLMemFenceExtendedKindESt4pairIKS1_N3spv19MemorySemanticsMaskEESt10_Select1stIS6_ESt4lessIS1_ESaIS6_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS6_ERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN7OCLUtil6OclExt4KindES2_St9_IdentityIS2_ESt4lessIS2_ESaIS2_EE16_M_insert_uniqueIRKS2_EESt4pairISt17_Rb_tree_iteratorIS2_EbEOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN7OCLUtil6OclExt4KindES2_St9_IdentityIS2_ESt4lessIS2_ESaIS2_EE24_M_get_insert_unique_posERKS2_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN7OCLUtil6OclExt4KindES2_St9_IdentityIS2_ESt4lessIS2_ESaIS2_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS2_ERKS2_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIN7OCLUtil6OclExt4KindESt4pairIKS2_N3spv10CapabilityEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS4_EESI_IJEEEEESt17_Rb_tree_iteratorIS7_ESt23_Rb_tree_const_iteratorIS7_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN7OCLUtil6OclExt4KindESt4pairIKS2_N3spv10CapabilityEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN7OCLUtil6OclExt4KindESt4pairIKS2_N3spv10CapabilityEESt10_Select1stIS7_ESt4lessIS2_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS4_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN7OCLUtil6OclExt4KindESt4pairIKS2_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISB_ESt4lessIS2_ESaISB_EE24_M_get_insert_unique_posERS4_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN7OCLUtil6OclExt4KindESt4pairIKS2_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISB_ESt4lessIS2_ESaISB_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISB_ERS4_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIN9OpenCLLIB11EntrypointsESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE24_M_get_insert_unique_posERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIN9OpenCLLIB11EntrypointsESt4pairIKS1_NSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEESt10_Select1stISA_ESt4lessIS1_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS3_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_St9_IdentityIS5_ESt4lessIS5_ESaIS5_EE16_M_insert_uniqueIRKS5_EESt4pairISt17_Rb_tree_iteratorIS5_EbEOT_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_St9_IdentityIS5_ESt4lessIS5_ESaIS5_EE16_M_insert_uniqueIS5_EESt4pairISt17_Rb_tree_iteratorIS5_EbEOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_St9_IdentityIS5_ESt4lessIS5_ESaIS5_EE24_M_get_insert_unique_posERKS5_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_St9_IdentityIS5_ESt4lessIS5_ESaIS5_EE4findERKS5_@Base 14
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N10SPIRVDebug11InstructionEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N10SPIRVDebug11InstructionEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv10CapabilityEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv10CapabilityEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv10DecorationEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv10DecorationEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv11LinkageTypeEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv11LinkageTypeEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv14FPRoundingModeEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv14FPRoundingModeEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv14GroupOperationEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv14GroupOperationEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv15AccessQualifierEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv15AccessQualifierEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv2OpEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv2OpEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv5ScopeEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 14
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv5ScopeEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 14
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv7BuiltInEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv7BuiltInEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv8internal25InternalJointMatrixLayoutEESt10_Select1stISB_ESt4lessIS5_ESaISB_EE24_M_get_insert_unique_posERS7_@Base 14
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N3spv8internal25InternalJointMatrixLayoutEESt10_Select1stISB_ESt4lessIS5_ESaISB_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISB_ERS7_@Base 14
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N5SPIRV11ExtensionIDEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N5SPIRV11ExtensionIDEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N5SPIRV14SPIRVErrorCodeEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N5SPIRV14SPIRVErrorCodeEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N5SPIRV19SPIRVExtInstSetKindEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N5SPIRV19SPIRVExtInstSetKindEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N7OCLUtil6OclExt4KindEESt10_Select1stISB_ESt4lessIS5_ESaISB_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N7OCLUtil6OclExt4KindEESt10_Select1stISB_ESt4lessIS5_ESaISB_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISB_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N9OpenCLLIB11EntrypointsEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N9OpenCLLIB11EntrypointsEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorISA_ERS7_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_jESt10_Select1stIS8_ESt4lessIS5_ESaIS8_EE24_M_get_insert_unique_posERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_jESt10_Select1stIS8_ESt4lessIS5_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS7_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIPN4llvm8FunctionES2_St9_IdentityIS2_ESt4lessIS2_ESaIS2_EE16_M_insert_uniqueIRKS2_EESt4pairISt17_Rb_tree_iteratorIS2_EbEOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_10DecorationEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE24_M_get_insert_unique_posERS6_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_10DecorationEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS6_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_12StorageClassEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE24_M_get_insert_unique_posERS6_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_12StorageClassEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS6_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_13ExecutionModeEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE24_M_get_insert_unique_posERS6_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_13ExecutionModeEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS6_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_14ExecutionModelEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE24_M_get_insert_unique_posERS6_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_14ExecutionModelEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS6_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_7BuiltInEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE24_M_get_insert_unique_posERS6_@Base 12
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_NS1_7BuiltInEESt10_Select1stIS8_ESt4lessIS4_ESaIS8_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS8_ERS6_@Base 12
++ (optional=templinst)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_S2_ESt10_Select1stIS7_ESt4lessIS4_ESaIS7_EE24_M_get_insert_unique_posERS6_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeISt6vectorIN3spv10CapabilityESaIS2_EESt4pairIKS4_S2_ESt10_Select1stIS7_ESt4lessIS4_ESaIS7_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS7_ERS6_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIjSt4pairIKjN17VectorComputeUtil11VCFloatTypeEESt10_Select1stIS4_ESt4lessIjESaIS4_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS1_EESF_IJEEEEESt17_Rb_tree_iteratorIS4_ESt23_Rb_tree_const_iteratorIS4_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIjSt4pairIKjN17VectorComputeUtil11VCFloatTypeEESt10_Select1stIS4_ESt4lessIjESaIS4_EE24_M_get_insert_unique_posERS1_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIjSt4pairIKjN17VectorComputeUtil11VCFloatTypeEESt10_Select1stIS4_ESt4lessIjESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS1_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIjSt4pairIKjN3spv2OpEESt10_Select1stIS4_ESt4lessIjESaIS4_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS1_EESF_IJEEEEESt17_Rb_tree_iteratorIS4_ESt23_Rb_tree_const_iteratorIS4_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIjSt4pairIKjN3spv2OpEESt10_Select1stIS4_ESt4lessIjESaIS4_EE24_M_get_insert_unique_posERS1_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIjSt4pairIKjN3spv2OpEESt10_Select1stIS4_ESt4lessIjESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS1_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIjSt4pairIKjN5SPIRV19SPIRVExtInstSetKindEESt10_Select1stIS4_ESt4lessIjESaIS4_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS1_EESF_IJEEEEESt17_Rb_tree_iteratorIS4_ESt23_Rb_tree_const_iteratorIS4_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIjSt4pairIKjN5SPIRV19SPIRVExtInstSetKindEESt10_Select1stIS4_ESt4lessIjESaIS4_EE24_M_get_insert_unique_posERS1_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIjSt4pairIKjN5SPIRV19SPIRVExtInstSetKindEESt10_Select1stIS4_ESt4lessIjESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS1_@Base 0
++ (optional=templinst|arch=!amd64 !arm64 !mips64el !ppc64el !riscv64 !sparc64 !x32)_ZNSt8_Rb_treeIjSt4pairIKjN7OCLUtil15OCLMemOrderKindEESt10_Select1stIS4_ESt4lessIjESaIS4_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS1_EESF_IJEEEEESt17_Rb_tree_iteratorIS4_ESt23_Rb_tree_const_iteratorIS4_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIjSt4pairIKjN7OCLUtil15OCLMemOrderKindEESt10_Select1stIS4_ESt4lessIjESaIS4_EE24_M_get_insert_unique_posERS1_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIjSt4pairIKjN7OCLUtil15OCLMemOrderKindEESt10_Select1stIS4_ESt4lessIjESaIS4_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS4_ERS1_@Base 0
++ (optional=templinst|arch=!mips64el !ppc64el !riscv64 !sparc64)_ZNSt8_Rb_treeIjjSt9_IdentityIjESt4lessIjESaIjEE16_M_insert_uniqueIRKjEESt4pairISt17_Rb_tree_iteratorIjEbEOT_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIjjSt9_IdentityIjESt4lessIjESaIjEE16_M_insert_uniqueIjEESt4pairISt17_Rb_tree_iteratorIjEbEOT_@Base 13
++ (optional=templinst)_ZNSt8_Rb_treeIjjSt9_IdentityIjESt4lessIjESaIjEE24_M_get_insert_unique_posERKj@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIlSt4pairIKllESt10_Select1stIS2_ESt4lessIlESaIS2_EE22_M_emplace_hint_uniqueIJRKSt21piecewise_construct_tSt5tupleIJRS1_EESD_IJEEEEESt17_Rb_tree_iteratorIS2_ESt23_Rb_tree_const_iteratorIS2_EDpOT_@Base 0
++ (optional=templinst)_ZNSt8_Rb_treeIlSt4pairIKllESt10_Select1stIS2_ESt4lessIlESaIS2_EE24_M_get_insert_unique_posERS1_@Base 0
++ (optional=templinst|arch=amd64 arm64 mips64el ppc64el riscv64 sparc64 x32)_ZNSt8_Rb_treeIlSt4pairIKllESt10_Select1stIS2_ESt4lessIlESaIS2_EE29_M_get_insert_hint_unique_posESt23_Rb_tree_const_iteratorIS2_ERS1_@Base 0
++ (optional=templinst)_ZNSt8__detail17__regex_algo_implIPKcSaINSt7__cxx119sub_matchIS2_EEEcNS3_12regex_traitsIcEEEEbT_S9_RNS3_13match_resultsIS9_T0_EERKNS3_11basic_regexIT1_T2_EENSt15regex_constants15match_flag_typeENS_20_RegexExecutorPolicyEb@Base 0
++ (optional=templinst)_ZNSt8__detail18__to_chars_10_implIjEEvPcjT_@Base 0
++ (optional=templinst)_ZNSt8__detail8_ScannerIcE12_M_eat_classEc@Base 0
++ (optional=templinst)_ZNSt8__detail8_ScannerIcE14_M_scan_normalEv@Base 0
++ (optional=templinst)_ZNSt8__detail8_ScannerIcE16_M_scan_in_braceEv@Base 0
++ (optional=templinst)_ZNSt8__detail8_ScannerIcE17_M_eat_escape_awkEv@Base 0
++ (optional=templinst)_ZNSt8__detail8_ScannerIcE18_M_eat_escape_ecmaEv@Base 0
++ (optional=templinst)_ZNSt8__detail8_ScannerIcE18_M_scan_in_bracketEv@Base 0
++ (optional=templinst)_ZNSt8__detail8_ScannerIcE19_M_eat_escape_posixEv@Base 0
++ (optional=templinst|arch=!mipsel)_ZNSt8__detail8_ScannerIcEC1EPKcS3_NSt15regex_constants18syntax_option_typeESt6locale@Base 0
++ (optional=templinst|arch=!mipsel)_ZNSt8__detail8_ScannerIcEC2EPKcS3_NSt15regex_constants18syntax_option_typeESt6locale@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE11_M_try_charEv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE12_M_assertionEv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE13_M_quantifierEv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE14_M_alternativeEv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE14_M_disjunctionEv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE16_M_cur_int_valueEi@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE18_M_expression_termILb0ELb0EEEbRNS4_13_BracketStateERNS_15_BracketMatcherIS3_XT_EXT0_EEE@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE18_M_expression_termILb0ELb1EEEbRNS4_13_BracketStateERNS_15_BracketMatcherIS3_XT_EXT0_EEE@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE18_M_expression_termILb1ELb0EEEbRNS4_13_BracketStateERNS_15_BracketMatcherIS3_XT_EXT0_EEE@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE18_M_expression_termILb1ELb1EEEbRNS4_13_BracketStateERNS_15_BracketMatcherIS3_XT_EXT0_EEE@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE21_M_bracket_expressionEv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE25_M_insert_bracket_matcherILb0ELb0EEEvb@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE25_M_insert_bracket_matcherILb0ELb1EEEvb@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE25_M_insert_bracket_matcherILb1ELb0EEEvb@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE25_M_insert_bracket_matcherILb1ELb1EEEvb@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE33_M_insert_character_class_matcherILb0ELb0EEEvv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE33_M_insert_character_class_matcherILb0ELb1EEEvv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE33_M_insert_character_class_matcherILb1ELb0EEEvv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE33_M_insert_character_class_matcherILb1ELb1EEEvv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEE7_M_atomEv@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEEC1EPKcS6_RKSt6localeNSt15regex_constants18syntax_option_typeE@Base 0
++ (optional=templinst)_ZNSt8__detail9_CompilerINSt7__cxx1112regex_traitsIcEEEC2EPKcS6_RKSt6localeNSt15regex_constants18syntax_option_typeE@Base 0
++ (optional=templinst)_ZNSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb0EE12_M_lookaheadEl@Base 0
++ (optional=templinst)_ZNSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb0EE16_M_rep_once_moreENS9_11_Match_modeEl@Base 0
++ (optional=templinst)_ZNSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb0EE17_M_handle_backrefENS9_11_Match_modeEl@Base 0
++ (optional=templinst)_ZNSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb0EE6_M_dfsENS9_11_Match_modeEl@Base 0
++ (optional=templinst)_ZNSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb1EE12_M_lookaheadEl@Base 0
++ (optional=templinst)_ZNSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb1EE16_M_rep_once_moreENS9_11_Match_modeEl@Base 0
++ (optional=templinst)_ZNSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb1EE17_M_handle_backrefENS9_11_Match_modeEl@Base 0
++ (optional=templinst)_ZNSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb1EE6_M_dfsENS9_11_Match_modeEl@Base 0
++ (optional=templinst)_ZNSt8__detail9_StateSeqINSt7__cxx1112regex_traitsIcEEE8_M_cloneEv@Base 0
++ (optional=templinst)_ZSt13binary_searchIN9__gnu_cxx17__normal_iteratorIPKcSt6vectorIcSaIcEEEEcEbT_S8_RKT0_@Base 0
++ (optional=templinst|subst)_ZSt17__rotate_adaptiveIN9__gnu_cxx17__normal_iteratorIPSt4pairIjjESt6vectorIS3_SaIS3_EEEES4_{ssize_t}ET_S9_S9_S9_T1_SA_T0_SA_@Base 13
++ (optional=templinst|arch=amd64 arm64 x32)_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_RKS8_@Base 0
++ (arch=armel riscv64)_ZTIN9__gnu_cxx7__mutexE@Base 13
++ _ZTINSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0ELb0EEE@Base 13
++ _ZTINSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0ELb1EEE@Base 13
++ _ZTINSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1ELb0EEE@Base 13
++ _ZTINSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1ELb1EEE@Base 13
++ _ZTINSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb1ELb0ELb0EEE@Base 13
++ _ZTINSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb1ELb0ELb1EEE@Base 13
++ _ZTINSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb1ELb1ELb0EEE@Base 13
++ _ZTINSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb1ELb1ELb1EEE@Base 13
++ _ZTINSt8__detail12_CharMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0EEE@Base 13
++ _ZTINSt8__detail12_CharMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1EEE@Base 13
++ _ZTINSt8__detail12_CharMatcherINSt7__cxx1112regex_traitsIcEELb1ELb0EEE@Base 13
++ _ZTINSt8__detail12_CharMatcherINSt7__cxx1112regex_traitsIcEELb1ELb1EEE@Base 13
++ _ZTINSt8__detail15_BracketMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0EEE@Base 13
++ _ZTINSt8__detail15_BracketMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1EEE@Base 13
++ _ZTINSt8__detail15_BracketMatcherINSt7__cxx1112regex_traitsIcEELb1ELb0EEE@Base 13
++ _ZTINSt8__detail15_BracketMatcherINSt7__cxx1112regex_traitsIcEELb1ELb1EEE@Base 13
++ (arch=armel riscv64)_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE1EE@Base 13
++ (arch=!armel !riscv64)_ZTISt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE@Base 13
++ (arch=armel riscv64)_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE1EE@Base 13
++ (arch=!armel !riscv64)_ZTISt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE@Base 13
++ (arch=armel armhf)_ZTISt19_Sp_make_shared_tag@Base 13
++ (arch=armel riscv64)_ZTISt23_Sp_counted_ptr_inplaceINSt8__detail4_NFAINSt7__cxx1112regex_traitsIcEEEESaIvELN9__gnu_cxx12_Lock_policyE1EE@Base 13
++ (arch=!armel !riscv64)_ZTISt23_Sp_counted_ptr_inplaceINSt8__detail4_NFAINSt7__cxx1112regex_traitsIcEEEESaIvELN9__gnu_cxx12_Lock_policyE2EE@Base 13
++ (arch=armel riscv64)_ZTSN9__gnu_cxx7__mutexE@Base 13
++ _ZTSNSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0ELb0EEE@Base 13
++ _ZTSNSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0ELb1EEE@Base 13
++ _ZTSNSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1ELb0EEE@Base 13
++ _ZTSNSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1ELb1EEE@Base 13
++ _ZTSNSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb1ELb0ELb0EEE@Base 13
++ _ZTSNSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb1ELb0ELb1EEE@Base 13
++ _ZTSNSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb1ELb1ELb0EEE@Base 13
++ _ZTSNSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb1ELb1ELb1EEE@Base 13
++ _ZTSNSt8__detail12_CharMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0EEE@Base 13
++ _ZTSNSt8__detail12_CharMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1EEE@Base 13
++ _ZTSNSt8__detail12_CharMatcherINSt7__cxx1112regex_traitsIcEELb1ELb0EEE@Base 13
++ _ZTSNSt8__detail12_CharMatcherINSt7__cxx1112regex_traitsIcEELb1ELb1EEE@Base 13
++ _ZTSNSt8__detail15_BracketMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0EEE@Base 13
++ _ZTSNSt8__detail15_BracketMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1EEE@Base 13
++ _ZTSNSt8__detail15_BracketMatcherINSt7__cxx1112regex_traitsIcEELb1ELb0EEE@Base 13
++ _ZTSNSt8__detail15_BracketMatcherINSt7__cxx1112regex_traitsIcEELb1ELb1EEE@Base 13
++ (arch=armel riscv64)_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE1EE@Base 13
++ (arch=!armel !riscv64)_ZTSSt11_Mutex_baseILN9__gnu_cxx12_Lock_policyE2EE@Base 13
++ (arch=armel riscv64)_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE1EE@Base 13
++ (arch=!armel !riscv64)_ZTSSt16_Sp_counted_baseILN9__gnu_cxx12_Lock_policyE2EE@Base 13
++ _ZTSSt19_Sp_make_shared_tag@Base 13
++ (arch=armel riscv64)_ZTSSt23_Sp_counted_ptr_inplaceINSt8__detail4_NFAINSt7__cxx1112regex_traitsIcEEEESaIvELN9__gnu_cxx12_Lock_policyE1EE@Base 13
++ (arch=!armel !riscv64)_ZTSSt23_Sp_counted_ptr_inplaceINSt8__detail4_NFAINSt7__cxx1112regex_traitsIcEEEESaIvELN9__gnu_cxx12_Lock_policyE2EE@Base 13
++ (arch=armel riscv64)_ZTVSt23_Sp_counted_ptr_inplaceINSt8__detail4_NFAINSt7__cxx1112regex_traitsIcEEEESaIvELN9__gnu_cxx12_Lock_policyE1EE@Base 0
++ (arch=!armel !riscv64)_ZTVSt23_Sp_counted_ptr_inplaceINSt8__detail4_NFAINSt7__cxx1112regex_traitsIcEEEESaIvELN9__gnu_cxx12_Lock_policyE2EE@Base 0
++ (optional=templinst)_ZZNKSt7__cxx1112regex_traitsIcE16lookup_classnameIPKcEENS1_10_RegexMaskET_S6_bE12__classnames@Base 0
++ (optional=templinst)_ZZNKSt7__cxx1112regex_traitsIcE18lookup_collatenameIPKcEENS_12basic_stringIcSt11char_traitsIcESaIcEEET_SA_E14__collatenames@Base 0
++ (optional=templinst)_ZZNKSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0ELb0EEclEcE5__nul@Base 0
++ (optional=templinst)_ZZNKSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb0ELb1EEclEcE5__nul@Base 0
++ (optional=templinst)_ZZNKSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1ELb0EEclEcE5__nul@Base 0
++ (optional=templinst)_ZZNKSt8__detail11_AnyMatcherINSt7__cxx1112regex_traitsIcEELb0ELb1ELb1EEclEcE5__nul@Base 0
++ (optional=templinst)_ZZNKSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb0EE10_M_is_wordEcE3__s@Base 0
++ (optional=templinst)_ZZNKSt8__detail9_ExecutorIPKcSaINSt7__cxx119sub_matchIS2_EEENS3_12regex_traitsIcEELb1EE10_M_is_wordEcE3__s@Base 0
++ _ZZNSt19_Sp_make_shared_tag5_S_tiEvE5__tag@Base 0
++ (optional=templinst)_ZZNSt8__detail18__to_chars_10_implIjEEvPcjT_E8__digits@Base 0
++ (optional=templinst|subst)_ZZNSt8__detail18__to_chars_10_implI{uint64_t}EEvPcjT_E8__digits@Base 13
++ (optional=templinst|arch=!powerpc !ppc64)_ZZNSt9once_flag18_Prepare_executionC4IZSt9call_onceIRFPvRN4llvm12PassRegistryEEJSt17reference_wrapperIS5_EEEvRS_OT_DpOT0_EUlvE_EERSC_ENUlvE_4_FUNEv@Base 0
diff --cc debian/llvm-spirv-15.install
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..d060cd803aea71fcd8d8d349464c304071872d6e
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/llvm-spirv-15.install
@@@ -1,0 -1,0 +1,1 @@@
++usr/bin/llvm-spirv-*
diff --cc debian/patches/series
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..bee3dc49bd729c6706d3d64885c0bb730f13493f
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/patches/series
@@@ -1,0 -1,0 +1,1 @@@
++visibility-hidden.patch
diff --cc debian/patches/visibility-hidden.patch
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..aee2fd723e4bc2089426314e18511420c59ac9b7
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/patches/visibility-hidden.patch
@@@ -1,0 -1,0 +1,92 @@@
++Author: Andreas Beckmann <anbe@debian.org>
++Description: reduce the amount of symbols exposed by the library
++
++--- a/CMakeLists.txt
+++++ b/CMakeLists.txt
++@@ -116,6 +116,9 @@ if(NOT SPIRV_TOOLS_FOUND)
++           "--spirv-tools-dis support.")
++ endif(NOT SPIRV_TOOLS_FOUND)
++ 
+++add_compile_options(-fvisibility=hidden)
+++add_compile_options($<$<COMPILE_LANGUAGE:CXX>:-fvisibility-inlines-hidden>)
+++
++ add_subdirectory(lib/SPIRV)
++ add_subdirectory(tools/llvm-spirv)
++ if(LLVM_SPIRV_INCLUDE_TESTS)
++--- a/include/LLVMSPIRVLib.h
+++++ b/include/LLVMSPIRVLib.h
++@@ -46,6 +46,8 @@
++ #include <iostream>
++ #include <string>
++ 
+++#pragma GCC visibility push(default)
+++
++ namespace llvm {
++ // Pass initialization functions need to be declared before inclusion of
++ // PassSupport.h.
++@@ -69,8 +71,12 @@ class ModulePass;
++ class FunctionPass;
++ } // namespace llvm
++ 
+++#pragma GCC visibility pop
+++
++ #include "llvm/IR/Module.h"
++ 
+++#pragma GCC visibility push(default)
+++
++ namespace SPIRV {
++ 
++ class SPIRVModule;
++@@ -224,4 +230,6 @@ FunctionPass *createSPIRVLowerBitCastToN
++ 
++ } // namespace llvm
++ 
+++#pragma GCC visibility pop
+++
++ #endif // SPIRV_H
++--- a/include/LLVMSPIRVOpts.h
+++++ b/include/LLVMSPIRVOpts.h
++@@ -48,6 +48,8 @@
++ #include <map>
++ #include <unordered_map>
++ 
+++#pragma GCC visibility push(default)
+++
++ namespace llvm {
++ class IntrinsicInst;
++ } // namespace llvm
++@@ -225,4 +227,6 @@ private:
++ 
++ } // namespace SPIRV
++ 
+++#pragma GCC visibility pop
+++
++ #endif // SPIRV_LLVMSPIRVOPTS_H
++--- a/lib/SPIRV/libSPIRV/SPIRVStream.cpp
+++++ b/lib/SPIRV/libSPIRV/SPIRVStream.cpp
++@@ -81,6 +81,7 @@ static void readQuotedString(std::istrea
++ }
++ 
++ #ifdef _SPIRV_SUPPORT_TEXT_FMT
+++__attribute__ ((visibility ("default")))
++ bool SPIRVUseTextFormat = false;
++ #endif
++ 
++--- a/lib/SPIRV/libSPIRV/SPIRVModule.cpp
+++++ b/lib/SPIRV/libSPIRV/SPIRVModule.cpp
++@@ -2120,6 +2120,7 @@ bool isSpirvBinary(const std::string &Im
++ 
++ #ifdef _SPIRV_SUPPORT_TEXT_FMT
++ 
+++__attribute__ ((visibility ("default")))
++ bool convertSpirv(std::istream &IS, std::ostream &OS, std::string &ErrMsg,
++                   bool FromText, bool ToText) {
++   auto SaveOpt = SPIRVUseTextFormat;
++@@ -2156,6 +2157,7 @@ bool isSpirvText(const std::string &Img)
++   return Magic == MagicNumber;
++ }
++ 
+++__attribute__ ((visibility ("default")))
++ bool convertSpirv(std::string &Input, std::string &Out, std::string &ErrMsg,
++                   bool ToText) {
++   auto FromText = isSpirvText(Input);
diff --cc debian/rules
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..2f93c5980bb3fd82910aff238dcde6e1094ccf24
new file mode 100755 (executable)
--- /dev/null
--- /dev/null
+++ b/debian/rules
@@@ -1,0 -1,0 +1,38 @@@
++#!/usr/bin/make -f
++
++export DEB_BUILD_MAINT_OPTIONS         = hardening=+all
++
++include /usr/share/dpkg/pkg-info.mk
++
++LLVM_VERSION   = $(shell sed -n -r '/^Build/,/^$$/s/.*llvm-([0-9]+)-dev.*/\1/p' debian/control)
++
++%:
++      dh $@ --builddir build/
++
++override_dh_auto_configure:
++      dh_auto_configure -- \
++              -DCMAKE_SKIP_RPATH=ON \
++              -DLLVM_EXTERNAL_SPIRV_HEADERS_SOURCE_DIR=/usr/include \
++              -DBUILD_SHARED_LIBS=ON \
++              -DLLVM_SPIRV_INCLUDE_TESTS=ON \
++              -DLLVM_EXTERNAL_LIT=/usr/lib/llvm-$(LLVM_VERSION)/build/utils/lit/lit.py \
++              -Wno-dev
++
++execute_after_dh_auto_install:
++      mv debian/tmp/usr/bin/llvm-spirv debian/tmp/usr/bin/llvm-spirv-$(LLVM_VERSION)
++
++ignore_test_failures   = $(if $(filter $(DEB_HOST_ARCH),amd64),,-)
++override_dh_auto_test:
++      $(ignore_test_failures)env LD_LIBRARY_PATH=$(LD_LIBRARY_PATH):$(CURDIR)/build/lib/SPIRV dh_auto_test
++
++
++update-symbols:
++      pkgkde-getbuildlogs
++      echo "pkgkde-symbolshelper batchpatch -v $(DEB_VERSION_EPOCH_UPSTREAM) $(DEB_SOURCE)_$(DEB_DISTRIBUTION)_logs/$(DEB_SOURCE)_$(DEB_VERSION)_*build"
++
++
++ifneq (,$(wildcard .git))
++upstream:
++      git remote show $@ >/dev/null 2>&1 || git remote add $@ $(shell sed -rn 's/Repository: //p' debian/upstream/metadata)
++      git fetch $@ --prune
++endif
diff --cc debian/source/format
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..163aaf8d82b6c54f23c45f32895dbdfdcc27b047
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/source/format
@@@ -1,0 -1,0 +1,1 @@@
++3.0 (quilt)
diff --cc debian/source/lintian-overrides
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..585d08df8da4df700d99071286396137c6ab0128
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/source/lintian-overrides
@@@ -1,0 -1,0 +1,3 @@@
++# test data
++very-long-line-length-in-source-file * > 512 [test/*.cl:*]
++very-long-line-length-in-source-file * > 512 [test/*.ll:*]
diff --cc debian/tests/control
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..3fa6006d8a78b7bb554bb995138e1736be6b38e2
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/tests/control
@@@ -1,0 -1,0 +1,29 @@@
++Tests: upstream-testsuite
++Architecture: amd64
++Depends:
++ @,
++ cmake,
++ g++,
++ pkgconf,
++ spirv-headers,
++ spirv-tools,
++ clang-15,
++ llvm-15-dev,
++Restrictions:
++ allow-stderr,
++
++Test-Command: debian/tests/upstream-testsuite
++Features: test-name=upstream-testsuite-flaky
++Architecture: !amd64
++Depends:
++ @,
++ cmake,
++ g++,
++ pkgconf,
++ spirv-headers,
++ spirv-tools,
++ clang-15,
++ llvm-15-dev,
++Restrictions:
++ allow-stderr,
++ flaky,
diff --cc debian/tests/upstream-testsuite
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..4d0e7cb277b7572bfbcf3c1b51d4b10e053d6957
new file mode 100755 (executable)
--- /dev/null
--- /dev/null
+++ b/debian/tests/upstream-testsuite
@@@ -1,0 -1,0 +1,18 @@@
++#!/bin/sh
++set -e -u -x
++LLVM_VERSION=$(sed -n -r '/^Build/,/^$/s/.*llvm-([0-9]+)-dev.*/\1/p' debian/control)
++cp -a . "$AUTOPKGTEST_TMP"
++cd "$AUTOPKGTEST_TMP"
++mkdir build
++cd build
++cmake \
++      -DLLVM_EXTERNAL_SPIRV_HEADERS_SOURCE_DIR=/usr/include \
++      -DLLVM_SPIRV_INCLUDE_TESTS=ON \
++      -DLLVM_EXTERNAL_LIT=/usr/lib/llvm-${LLVM_VERSION}/build/utils/lit/lit.py \
++      -Wno-dev \
++      ..
++make --touch
++rm -f tools/llvm-spirv/llvm-spirv
++cp /usr/bin/llvm-spirv-${LLVM_VERSION} tools/llvm-spirv/llvm-spirv
++make -C test clean
++make test
diff --cc debian/upstream/metadata
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..1c0018d848b29aceb10d931dca451e1dcf711319
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/upstream/metadata
@@@ -1,0 -1,0 +1,4 @@@
++Bug-Database: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues
++Bug-Submit: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/new
++Repository: https://github.com/KhronosGroup/SPIRV-LLVM-Translator.git
++Repository-Browse: https://github.com/KhronosGroup/SPIRV-LLVM-Translator
diff --cc debian/watch
index 0000000000000000000000000000000000000000,0000000000000000000000000000000000000000..09845d74ae1b8de6c878d45d3d1e7d8b9cebb808
new file mode 100644 (file)
--- /dev/null
--- /dev/null
+++ b/debian/watch
@@@ -1,0 -1,0 +1,5 @@@
++version=4
++
++opts="filenamemangle=s%(?:.*?)?v?(\d[\d.]*)\.tar\.gz%spirv-llvm-translator-$1.tar.gz%" \
++   https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tags \
++   (?:.*?/)?v?(15\.[\d.]*)\.tar\.gz
Unnamed repository; edit this file 'description' to name the repository.