temp += post_update;
vcpu_set_gr(vcpu,inst.M15.r3,temp,0);
- vmx_vcpu_increment_iip(vcpu);
+ vcpu_increment_iip(vcpu);
return;
}
// Floating-point Load Pair + Imm ldfp8 M12
vcpu_set_fpreg(vcpu,inst.M12.f2,&v);
padr += 8;
vcpu_set_gr(vcpu,inst.M12.r3,padr,0);
- vmx_vcpu_increment_iip(vcpu);
+ vcpu_increment_iip(vcpu);
return;
- }
+ }
else{
panic_domain
(NULL,"This memory access instr can't be emulated: %lx pc=%lx\n ",
*/
}
}
- vmx_vcpu_increment_iip(vcpu);
+ vcpu_increment_iip(vcpu);
}
if (vector == IA64_FP_FAULT_VECTOR) {
status = handle_fpu_swa(1, regs, isr);
if (!status) {
- vmx_vcpu_increment_iip(vcpu);
+ vcpu_increment_iip(vcpu);
return;
} else if (IA64_RETRY == status)
return;
if (!status)
return;
else if (IA64_RETRY == status) {
- vmx_vcpu_decrement_iip(vcpu);
+ vcpu_decrement_iip(vcpu);
return;
}
}
/* Allow hypercalls only when cpl = 0. */
if (iim == d->arch.breakimm) {
ia64_hypercall(regs);
- vmx_vcpu_increment_iip(v);
+ vcpu_increment_iip(v);
return IA64_NO_FAULT;
}
else if(iim == DOMN_PAL_REQUEST){
pal_emul(v);
- vmx_vcpu_increment_iip(v);
+ vcpu_increment_iip(v);
return IA64_NO_FAULT;
}else if(iim == DOMN_SAL_REQUEST){
sal_emul(v);
- vmx_vcpu_increment_iip(v);
+ vcpu_increment_iip(v);
return IA64_NO_FAULT;
}
}
return ;
}
-/* Adjust slot both in pt_regs and vpd, upon vpsr.ri which
- * should have sync with ipsr in entry.
- *
- * Clear some bits due to successfully emulation.
- */
-IA64FAULT vmx_vcpu_increment_iip(VCPU *vcpu)
-{
- // TODO: trap_bounce?? Eddie
- REGS *regs = vcpu_regs(vcpu);
- IA64_PSR *ipsr = (IA64_PSR *)®s->cr_ipsr;
-
- if (ipsr->ri == 2) {
- ipsr->ri = 0;
- regs->cr_iip += 16;
- } else {
- ipsr->ri++;
- }
-
- ipsr->val &=
- (~ (IA64_PSR_ID |IA64_PSR_DA | IA64_PSR_DD |
- IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA
- ));
-
- return (IA64_NO_FAULT);
-}
-
-
-IA64FAULT vmx_vcpu_decrement_iip(VCPU *vcpu)
-{
- REGS *regs = vcpu_regs(vcpu);
- IA64_PSR *ipsr = (IA64_PSR *)®s->cr_ipsr;
-
- if (ipsr->ri == 0) {
- ipsr->ri = 2;
- regs->cr_iip -= 16;
- } else {
- ipsr->ri--;
- }
- return (IA64_NO_FAULT);
-}
-
-
IA64FAULT vmx_vcpu_cover(VCPU *vcpu)
{
REGS *regs = vcpu_regs(vcpu);
return (IA64_NO_FAULT);
}
-
struct virtual_platform_def *
vmx_vcpu_get_plat(VCPU *vcpu)
{
return &(vcpu->domain->arch.vmx_platform);
}
-
-
IA64FAULT vmx_vcpu_set_rr(VCPU *vcpu, u64 reg, u64 val)
{
ia64_rr oldrr,newrr;
#endif
if ( status == IA64_NO_FAULT && cause !=EVENT_RFI ) {
- vmx_vcpu_increment_iip(vcpu);
+ vcpu_increment_iip(vcpu);
}
recover_if_physical_mode(vcpu);
return IA64_NO_FAULT;
}
+IA64FAULT vcpu_decrement_iip(VCPU * vcpu)
+{
+ REGS *regs = vcpu_regs(vcpu);
+ struct ia64_psr *ipsr = (struct ia64_psr *)®s->cr_ipsr;
+
+ if (ipsr->ri == 0) {
+ ipsr->ri = 2;
+ regs->cr_iip -= 16;
+ } else
+ ipsr->ri--;
+
+ return IA64_NO_FAULT;
+}
+
IA64FAULT vcpu_set_ifa(VCPU * vcpu, u64 val)
{
PSCB(vcpu, ifa) = val;
extern IA64FAULT vcpu_get_isr(VCPU * vcpu, u64 * pval);
extern IA64FAULT vcpu_get_iip(VCPU * vcpu, u64 * pval);
extern IA64FAULT vcpu_increment_iip(VCPU * vcpu);
+extern IA64FAULT vcpu_decrement_iip(VCPU * vcpu);
extern IA64FAULT vcpu_get_ifa(VCPU * vcpu, u64 * pval);
extern IA64FAULT vcpu_get_itir(VCPU * vcpu, u64 * pval);
extern unsigned long vcpu_get_itir_on_fault(VCPU * vcpu, u64 ifa);
size_t s);
extern void memwrite_p(VCPU * vcpu, u64 * src, u64 * dest, size_t s);
extern void vcpu_load_kernel_regs(VCPU * vcpu);
-extern IA64FAULT vmx_vcpu_increment_iip(VCPU * vcpu);
-extern IA64FAULT vmx_vcpu_decrement_iip(VCPU * vcpu);
extern void vmx_switch_rr7(unsigned long, shared_info_t *, void *, void *,
void *);