Downloaded from:
https://patchwork.ozlabs.org/project/uboot/patch/
20210406151059.
1187379-1-icenowy@aosc.io
Downloaded from:
https://patchwork.ozlabs.org/project/uboot/patch/
20210406151059.
1187379-1-icenowy@aosc.io
From: Icenowy Zheng <icenowy@aosc.io>
To: Simon Glass <sjg@chromium.org>, Kever Yang <kever.yang@rock-chips.com>,
Frank Wang <frank.wang@rock-chips.com>,
Jagan Teki <jagan@amarulasolutions.com>
Cc: u-boot@lists.denx.de,
Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH] phy: rockchip: inno-usb2: fix hang when multiple controllers
exit
Date: Tue, 6 Apr 2021 23:10:59 +0800
Message-Id: <
20210406151059.
1187379-1-icenowy@aosc.io>
The OHCI and EHCI controllers are both bound to the same PHY. They will
both do init and power_on operations when the controller is brought up
and both do power_off and exit when the controller is stopped. However,
the PHY uclass of U-Boot is not as sane as we thought -- they won't
maintain a status mark for PHYs, and thus the functions of the PHYs
could be called for multiple times. Calling init/power_on for multiple
times have no severe problems, however calling power_off/exit for
multiple times have a problem -- the first exit call will stop the PHY
clock, and power_off/exit calls after it still trying to write to PHY
registers. The write operation to PHY registers will fail because clock
is already stopped.
Adapt the count mechanism from phy-sun4i-usb to both init/exit and
power_on/power_off functions to phy-rockchip-inno-usb2 to fix this
problem. With this stopping USB controllers (manually or before booting
a kernel) will work.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Fixes: ac97a9ece14e ("phy: rockchip: Add Rockchip USB2PHY driver")
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Gbp-Pq: Topic rockchip
Gbp-Pq: Name rockchip-inno-usb.patch
void *reg_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
+ int init_count;
+ int power_on_count;
};
static inline int property_enable(void *reg_base,
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+ priv->power_on_count++;
+ if (priv->power_on_count != 1)
+ return 0;
+
property_enable(priv->reg_base, &port_cfg->phy_sus, false);
/* waiting for the utmi_clk to become stable */
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+ priv->power_on_count--;
+ if (priv->power_on_count != 0)
+ return 0;
+
property_enable(priv->reg_base, &port_cfg->phy_sus, true);
return 0;
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
int ret;
+ priv->init_count++;
+ if (priv->init_count != 1)
+ return 0;
+
ret = clk_enable(&priv->phyclk);
if (ret) {
dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ priv->init_count--;
+ if (priv->init_count != 0)
+ return 0;
+
clk_disable(&priv->phyclk);
return 0;
return ret;
}
+ priv->power_on_count = 0;
+ priv->init_count = 0;
+
return 0;
}