x86, cpufreq: Allow dom0 kernel to govern cpufreq via the Intel

Enahanced SpeedStep MSR.
From: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 8ccbeee2c6761b333b3083e636060abddf23a471..0aa8c8ba545b015445531dd2f08e52c88e7e3cca 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1773,6 +1773,12 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
                  wrmsr_safe(regs->ecx, eax, edx) )
                 goto fail;
             break;
+        case MSR_IA32_PERF_CTL:
+            if ( (cpufreq_controller != FREQCTL_dom0_kernel) ||
+                 (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) ||
+                 wrmsr_safe(regs->ecx, eax, edx) )
+                goto fail;
+            break;
         default:
             if ( wrmsr_hypervisor_regs(regs->ecx, eax, edx) )
                 break;