* ARMv8 (DDI 0487A.d): D7.2.1
*/
case HSR_SYSREG_ACTLR_EL1:
- if ( psr_mode_is_user(regs) )
+ if ( regs_mode_is_user(regs) )
return inject_undef_exception(regs, hsr);
if ( hsr.sysreg.read )
set_user_reg(regs, regidx, v->arch.actlr);
return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1);
case HSR_SYSREG_PMUSERENR_EL0:
/* RO at EL0. RAZ/WI at EL1 */
- if ( psr_mode_is_user(regs) )
+ if ( regs_mode_is_user(regs) )
return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0);
else
return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1);
#ifdef CONFIG_ARM_32
#define hyp_mode(r) psr_mode((r)->cpsr,PSR_MODE_HYP)
-#define psr_mode_is_user(r) usr_mode(r)
+#define regs_mode_is_user(r) usr_mode(r)
#else
#define hyp_mode(r) (psr_mode((r)->cpsr,PSR_MODE_EL2h) || \
psr_mode((r)->cpsr,PSR_MODE_EL2t))
* Trap may have been taken from EL0, which might be in AArch32 usr
* mode, or in AArch64 mode (PSR_MODE_EL0t).
*/
-#define psr_mode_is_user(r) \
+#define regs_mode_is_user(r) \
(psr_mode((r)->cpsr,PSR_MODE_EL0t) || usr_mode(r))
#endif
.len = instr_len,
};
- if ( psr_mode_is_user(regs) )
+ if ( regs_mode_is_user(regs) )
esr.ec = prefetch
? HSR_EC_INSTR_ABORT_LOWER_EL : HSR_EC_DATA_ABORT_LOWER_EL;
else
vcpu_pause(v); /* acceptably dangerous */
vcpu_show_registers(v);
- if ( !psr_mode_is_user(&v->arch.cpu_info->guest_cpu_user_regs) )
+ if ( !regs_mode_is_user(&v->arch.cpu_info->guest_cpu_user_regs) )
show_guest_stack(v, &v->arch.cpu_info->guest_cpu_user_regs);
vcpu_unpause(v);
multi->args[2], multi->args[3],
multi->args[4]);
- return likely(!psr_mode_is_user(guest_cpu_user_regs()))
+ return likely(!regs_mode_is_user(guest_cpu_user_regs()))
? mc_continue : mc_preempt;
}
{
ASSERT((min_el == 0) || (min_el == 1));
- if ( min_el > 0 && psr_mode_is_user(regs) )
+ if ( min_el > 0 && regs_mode_is_user(regs) )
return inject_undef_exception(regs, hsr);
if ( read )
{
ASSERT((min_el == 0) || (min_el == 1));
- if ( min_el > 0 && psr_mode_is_user(regs) )
+ if ( min_el > 0 && regs_mode_is_user(regs) )
return inject_undef_exception(regs, hsr);
if ( read )
{
ASSERT((min_el == 0) || (min_el == 1));
- if ( min_el > 0 && psr_mode_is_user(regs) )
+ if ( min_el > 0 && regs_mode_is_user(regs) )
return inject_undef_exception(regs, hsr);
if ( !read )
* ARMv8 (DDI 0487A.d): G6.2.1
*/
case HSR_CPREG32(ACTLR):
- if ( psr_mode_is_user(regs) )
+ if ( regs_mode_is_user(regs) )
return inject_undef_exception(regs, hsr);
if ( cp32.read )
set_user_reg(regs, regidx, v->arch.actlr);
*/
case HSR_CPREG32(PMUSERENR):
/* RO at EL0. RAZ/WI at EL1 */
- if ( psr_mode_is_user(regs) )
+ if ( regs_mode_is_user(regs) )
return handle_ro_raz(regs, regidx, cp32.read, hsr, 0);
else
return handle_raz_wi(regs, regidx, cp32.read, hsr, 1);
* CNTKCTL_EL1_ bit name which gates user access
*/
#define ACCESS_ALLOWED(regs, user_gate) \
- ( !psr_mode_is_user(regs) || \
+ ( !regs_mode_is_user(regs) || \
(READ_SYSREG(CNTKCTL_EL1) & CNTKCTL_EL1_##user_gate) )
static void phys_timer_expired(void *data)