case 0x80000005: /* AMD L1 cache/TLB info (dumped by Intel policy) */
case 0x80000006: /* AMD L2/3 cache/TLB info ; Intel L2 cache features */
case 0x8000000a: /* AMD SVM feature bits */
+ case 0x80000019: /* AMD 1G TLB */
+ case 0x8000001a: /* AMD perf hints */
case 0x8000001c: /* AMD lightweight profiling */
break;
p->extd.raw[0x8].c &= 0x0003f0ff;
p->extd.raw[0x9] = EMPTY_LEAF;
+
+ zero_leaves(p->extd.raw, 0xb, 0x18);
break;
}
}
if ( !p->extd.svm )
p->extd.raw[0xa] = EMPTY_LEAF;
+
+ if ( !p->extd.page1gb )
+ p->extd.raw[0x19] = EMPTY_LEAF;
}
int init_domain_cpuid_policy(struct domain *d)
case 0x2 ... 0x3:
case 0x7 ... 0x9:
case 0xc ... XSTATE_CPUID:
- case 0x80000000 ... 0x8000000a:
+ case 0x80000000 ... 0x8000001a:
ASSERT_UNREACHABLE();
/* Now handled in guest_cpuid(). */
}
case 0x2 ... 0x3:
case 0x7 ... 0x9:
case 0xc ... XSTATE_CPUID:
- case 0x80000000 ... 0x8000000a:
+ case 0x80000000 ... 0x8000001a:
ASSERT_UNREACHABLE();
/* Now handled in guest_cpuid(). */
}
default:
goto legacy;
- case 0x80000000 ... 0x8000000a:
+ case 0x80000000 ... 0x8000001a:
*res = p->extd.raw[leaf & 0xffff];
break;
}