x86, amd, hvm: pass through one more cpuid cache description leaf

Add a missing CPUID leaf that contains AMD-specific cache info.
Without this, Windows can spin trying to prefetch memory buffers using
a stride length of zero.

Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>

diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 2f08182bfda3f4e4b439cbf726d02129b4a34985..9a1aa896998ae07e285c6188a5e2ecc1e181c072 100644 (file)
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -137,6 +137,10 @@ static void intel_xc_cpuid_policy(
                     (is_64bit ? bitmaskof(X86_FEATURE_SYSCALL) : 0));
         break;
     }
+
+    case 0x80000005:
+        regs[0] = regs[1] = regs[2] = 0;
+        break;
     }
 }
 
@@ -210,12 +214,13 @@ static void xc_cpuid_hvm_policy(
         regs[1] = regs[2] = regs[3] = 0;
         break;
 
-    case 0x00000002:
-    case 0x00000004:
-    case 0x80000002:
-    case 0x80000003:
-    case 0x80000004:
-    case 0x80000006:
+    case 0x00000002: /* Intel cache info (dumped by AMD policy) */
+    case 0x00000004: /* Intel cache info (dumped by AMD policy) */
+    case 0x80000002: /* Processor name string */
+    case 0x80000003: /* ... continued         */
+    case 0x80000004: /* ... continued         */
+    case 0x80000005: /* AMD L1 cache/TLB info (dumped by Intel policy) */
+    case 0x80000006: /* AMD L2/3 cache/TLB info ; Intel L2 cache features */
         break;
 
     default: