x86/cpuid: detect null segment behaviour on Zen2 CPUs

All Zen2 CPUs actually have this behaviour, but the CPUID bit couldn't
be introduced into Zen2 due to a lack of leaves. So, it was added in a
new leaf in Zen3. Nonetheless, hypervisors can synthesize the CPUID
bit in software.

So, Xen probes for NSCB (NullSelectorClearsBit) and
synthesizes the bit, if the behaviour is present.

Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Jane Malalane <jane.malalane@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 2260eef3aab50315fe802f01d901c6e13dc68778..cb1286148179305bd22dbb8e848763cda3d5ee9f 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -681,6 +681,19 @@ void amd_init_lfence(struct cpuinfo_x86 *c)
                          c->x86_capability);
 }
 
+void __init detect_zen2_null_seg_behaviour(void)
+{
+       uint64_t base;
+
+       wrmsrl(MSR_FS_BASE, 1);
+       asm volatile ( "mov %0, %%fs" :: "rm" (0) );
+       rdmsrl(MSR_FS_BASE, base);
+
+       if (base == 0)
+               setup_force_cpu_cap(X86_FEATURE_NSCB);
+
+}
+
 static void init_amd(struct cpuinfo_x86 *c)
 {
        u32 l, h;
@@ -731,6 +744,11 @@ static void init_amd(struct cpuinfo_x86 *c)
        else /* Implicily "== 0x10 || >= 0x12" by being 64bit. */
                amd_init_lfence(c);
 
+       /* Probe for NSCB on Zen2 CPUs when not virtualised */
+       if (!cpu_has_hypervisor && !cpu_has_nscb && c == &boot_cpu_data &&
+           c->x86 == 0x17)
+               detect_zen2_null_seg_behaviour();
+
        /*
         * If the user has explicitly chosen to disable Memory Disambiguation
         * to mitigiate Speculative Store Bypass, poke the appropriate MSR.

diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index 1ac3b2867a04f3a6580661577c59ba90397c806a..0dd1b762ff98dfa4ef09926cd223ddc43800237f 100644 (file)
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -21,3 +21,4 @@ extern bool detect_extended_topology(struct cpuinfo_x86 *c);
 void early_init_amd(struct cpuinfo_x86 *c);
 void amd_log_freq(const struct cpuinfo_x86 *c);
 void amd_init_lfence(struct cpuinfo_x86 *c);
+void detect_zen2_null_seg_behaviour(void);

diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c
index 67e23c5df9e3a927d53b40acc7f44a0d9f4b70ea..d7a04af2bbbdec27f3f768c8d413a3a5a66aa9de 100644 (file)
--- a/xen/arch/x86/cpu/hygon.c
+++ b/xen/arch/x86/cpu/hygon.c
@@ -34,6 +34,11 @@ static void init_hygon(struct cpuinfo_x86 *c)
 
        amd_init_lfence(c);
 
+       /* Probe for NSCB on Zen2 CPUs when not virtualised */
+       if (!cpu_has_hypervisor && !cpu_has_nscb && c == &boot_cpu_data &&
+           c->x86 == 0x18)
+               detect_zen2_null_seg_behaviour();
+
        /*
         * If the user has explicitly chosen to disable Memory Disambiguation
         * to mitigiate Speculative Store Bypass, poke the appropriate MSR.

diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 5f6b83f71c2108c8ebc79707068d62ef8e7b2954..4faf9bff298632053bd363710055f9dd6ffdb6a4 100644 (file)
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -146,6 +146,7 @@
 #define cpu_has_cpuid_faulting  boot_cpu_has(X86_FEATURE_CPUID_FAULTING)
 #define cpu_has_aperfmperf      boot_cpu_has(X86_FEATURE_APERFMPERF)
 #define cpu_has_lfence_dispatch boot_cpu_has(X86_FEATURE_LFENCE_DISPATCH)
+#define cpu_has_nscb            boot_cpu_has(X86_FEATURE_NSCB)
 #define cpu_has_xen_lbr         boot_cpu_has(X86_FEATURE_XEN_LBR)
 #define cpu_has_xen_shstk       boot_cpu_has(X86_FEATURE_XEN_SHSTK)