x86/Intel: drop another 32-bit leftover

None of the models MISC_ENABLE MSR access is excluded for support 64-bit
mode - drop the conditional from early_init_intel(). Also convert
pointless rdmsr_safe() elsewhere to rdmsrl().

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index d3145c01170615645ae63d18a51a26ba13eb6f77..8311952f1f131e8194fec8f7f51dafa33304eaa0 100644 (file)
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -283,31 +283,29 @@ static void __init noinline intel_init_levelling(void)
 
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
+       u64 misc_enable, disable;
+
        /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
        if (c->x86 == 15 && c->x86_cache_alignment == 64)
                c->x86_cache_alignment = 128;
 
        /* Unmask CPUID levels and NX if masked: */
-       if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
-               u64 misc_enable, disable;
-
-               rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+       rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 
-               disable = misc_enable & (MSR_IA32_MISC_ENABLE_LIMIT_CPUID |
-                                        MSR_IA32_MISC_ENABLE_XD_DISABLE);
-               if (disable) {
-                       wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
-                       bootsym(trampoline_misc_enable_off) |= disable;
-               }
+       disable = misc_enable & (MSR_IA32_MISC_ENABLE_LIMIT_CPUID |
+                                MSR_IA32_MISC_ENABLE_XD_DISABLE);
+       if (disable) {
+               wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
+               bootsym(trampoline_misc_enable_off) |= disable;
+       }
 
-               if (disable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)
-                       printk(KERN_INFO "revised cpuid level: %d\n",
-                              cpuid_eax(0));
-               if (disable & MSR_IA32_MISC_ENABLE_XD_DISABLE) {
-                       write_efer(read_efer() | EFER_NX);
-                       printk(KERN_INFO
-                              "re-enabled NX (Execute Disable) protection\n");
-               }
+       if (disable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)
+               printk(KERN_INFO "revised cpuid level: %d\n",
+                      cpuid_eax(0));
+       if (disable & MSR_IA32_MISC_ENABLE_XD_DISABLE) {
+               write_efer(read_efer() | EFER_NX);
+               printk(KERN_INFO
+                      "re-enabled NX (Execute Disable) protection\n");
        }
 
        /* CPUID workaround for Intel 0F33/0F34 CPU */

diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 2f9264548ab82be6f837dd12fba9c89ef603ff01..6115840daef66b604f2529fb8ba38f83ab47ce19 100644 (file)
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -928,8 +928,7 @@ static int read_msr(unsigned int reg, uint64_t *val,
         goto normal;
 
     case MSR_IA32_MISC_ENABLE:
-        if ( rdmsr_safe(reg, *val) )
-            break;
+        rdmsrl(reg, *val);
         *val = guest_misc_enable(*val);
         return X86EMUL_OKAY;
 
@@ -1098,8 +1097,7 @@ static int write_msr(unsigned int reg, uint64_t val,
         return X86EMUL_OKAY;
 
     case MSR_IA32_MISC_ENABLE:
-        if ( rdmsr_safe(reg, temp) )
-            break;
+        rdmsrl(reg, temp);
         if ( val != guest_misc_enable(temp) )
             goto invalid;
         return X86EMUL_OKAY;