# define ARCH_PROCESSOR "bfin"
#elif defined(Q_PROCESSOR_WASM)
# define ARCH_PROCESSOR "wasm"
+#elif defined(Q_PROCESSOR_HPPA)
+# define ARCH_PROCESSOR "hppa"
#elif defined(Q_PROCESSOR_X86_32)
# define ARCH_PROCESSOR "i386"
#elif defined(Q_PROCESSOR_X86_64)
\sa QSysInfo::buildCpuArchitecture()
*/
+/*!
+ \macro Q_PROCESSOR_HPPA
+ \relates <QtGlobal>
+
+ Defined if the application is compiled for PA-RISC processors.
+
+ \sa QSysInfo::buildCpuArchitecture()
+*/
+
/*!
\macro Q_PROCESSOR_IA64
\relates <QtGlobal>
// # define Q_PROCESSOR_BLACKFIN
// # define Q_BYTE_ORDER Q_LITTLE_ENDIAN
+/*
+ PA-RISC family, no revisions or variants
+
+ PA-RISC is big-endian.
+*/
+#elif defined(__hppa__)
+# define Q_PROCESSOR_HPPA
+# define Q_BYTE_ORDER Q_BIG_ENDIAN
+
/*
X86 family, known variants: 32- and 64-bit
EM_AARCH64
#elif defined(Q_PROCESSOR_BLACKFIN)
EM_BLACKFIN
+#elif defined(Q_PROCESSOR_HPPA)
+ EM_PARISC
#elif defined(Q_PROCESSOR_IA64)
EM_IA_64
#elif defined(Q_PROCESSOR_MIPS)
#endif
case EM_IA_64: d << ", IA-64"; break;
case EM_MIPS: d << ", MIPS"; break;
+ case EM_PARISC: d << ", HPPA"; break;
case EM_PPC: d << ", PowerPC"; break;
case EM_PPC64: d << ", PowerPC 64-bit"; break;
#ifdef EM_RISCV