c->isa64.bits[0] = READ_SYSREG(ID_AA64ISAR0_EL1);
c->isa64.bits[1] = READ_SYSREG(ID_AA64ISAR1_EL1);
+ c->isa64.bits[2] = READ_SYSREG(ID_AA64ISAR2_EL1);
c->zfr64.bits[0] = READ_SYSREG(ID_AA64ZFR0_EL1);
#ifndef ID_DFR1_EL1
#define ID_DFR1_EL1 S3_0_C0_C3_5
#endif
+#ifndef ID_AA64ISAR2_EL1
+#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
+#endif
/* ID registers (imported from arm64/include/asm/sysreg.h in Linux) */
#define ID_AA64ISAR1_GPI_NI 0x0
#define ID_AA64ISAR1_GPI_IMP_DEF 0x1
+/* id_aa64isar2 */
+#define ID_AA64ISAR2_CLEARBHB_SHIFT 28
+
/* id_aa64pfr0 */
#define ID_AA64PFR0_CSV3_SHIFT 60
#define ID_AA64PFR0_CSV2_SHIFT 56
#define ID_AA64MMFR0_PARANGE_52 0x6
/* id_aa64mmfr1 */
+#define ID_AA64MMFR1_ECBHB_SHIFT 60
#define ID_AA64MMFR1_ETS_SHIFT 36
#define ID_AA64MMFR1_TWED_SHIFT 32
#define ID_AA64MMFR1_XNX_SHIFT 28
unsigned long lo:4;
unsigned long pan:4;
unsigned long __res1:8;
- unsigned long __res2:32;
+ unsigned long __res2:28;
+ unsigned long ecbhb:4;
unsigned long __res3:64;
};
} mm64;
union {
- register_t bits[2];
+ register_t bits[3];
struct {
/* ISAR0 */
unsigned long __res0:4;
unsigned long dgh:4;
unsigned long i8mm:4;
unsigned long __res2:8;
+
+ /* ISAR2 */
+ unsigned long __res3:28;
+ unsigned long clearbhb:4;
+
+ unsigned long __res4:32;
};
} isa64;