pl011: preserve RTS and DTR signal on UART init

Although we do not support hardware flow control in the Xen driver
for the PL011 UART, the other end may be configured to use it.
In this case it waits in vain for the RTS signal to be asserted by
the host and will never transmit any characters.
So we leave RTS and DTR as they had been setup before.
This fixes the UART input on Calxeda Midway, which uses hardware
flow control for the serial-over-LAN functionality.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>

diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index 3ec6e109d76744f353bb7862615d47d06dbd60b1..3386e2bc284cb96ef71da41e28fe80739afb537e 100644 (file)
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -85,6 +85,7 @@ static void __init pl011_init_preirq(struct serial_port *port)
 {
     struct pl011 *uart = port->uart;
     unsigned int divisor;
+    unsigned int cr;
 
     /* No interrupts, please. */
     pl011_write(uart, IMSC, 0);
@@ -120,8 +121,10 @@ static void __init pl011_init_preirq(struct serial_port *port)
     pl011_write(uart, IMSC, 0);
     pl011_write(uart, ICR, ALLI);
 
-    /* Enable the UART for RX and TX; no flow ctrl */
-    pl011_write(uart, CR, RXE | TXE | UARTEN);
+    /* Enable the UART for RX and TX; keep RTS and DTR */
+    cr = pl011_read(uart, CR);
+    cr &= RTS | DTR;
+    pl011_write(uart, CR, cr | RXE | TXE | UARTEN);
 }
 
 static void __init pl011_init_postirq(struct serial_port *port)

diff --git a/xen/include/asm-arm/pl011-uart.h b/xen/include/asm-arm/pl011-uart.h
index 3332c51fef9a131fd9bf9f60d5f0f0d6f9ca5f13..123f4777652a64d4b633deaabca34ae5524162dc 100644 (file)
--- a/xen/include/asm-arm/pl011-uart.h
+++ b/xen/include/asm-arm/pl011-uart.h
@@ -38,6 +38,10 @@
 #define DMACR  (0x48)
 
 /* CR bits */
+#define CTSEN  (1<<15) /* automatic CTS hardware flow control */
+#define RTSEN  (1<<14) /* automatic RTS hardware flow control */
+#define RTS    (1<<11) /* RTS signal */
+#define DTR    (1<<10) /* DTR signal */
 #define RXE    (1<<9) /* Receive enable */
 #define TXE    (1<<8) /* Transmit enable */
 #define UARTEN (1<<0) /* UART enable */