{
u32 period;
struct hvm_hw_pit_channel *s = &pit->hw.channels[channel];
- struct periodic_time *pt = &pit->pt[channel];
struct vcpu *v = vpit_vcpu(pit);
ASSERT(spin_is_locked(&pit->lock));
{
case 2:
/* Periodic timer. */
- create_periodic_time(v, pt, period, 0, 0, pit_time_fired,
+ create_periodic_time(v, &pit->pt0, period, 0, 0, pit_time_fired,
&pit->count_load_time[channel]);
break;
case 1:
/* One-shot timer. */
- create_periodic_time(v, pt, period, 0, 1, pit_time_fired,
+ create_periodic_time(v, &pit->pt0, period, 0, 1, pit_time_fired,
&pit->count_load_time[channel]);
break;
default:
- destroy_periodic_time(pt);
+ destroy_periodic_time(&pit->pt0);
break;
}
}
void pit_stop_channel0_irq(PITState *pit)
{
spin_lock(&pit->lock);
- destroy_periodic_time(&pit->pt[0]);
+ destroy_periodic_time(&pit->pt0);
spin_unlock(&pit->lock);
}
printk("pit 0x%x.\n", s->gate);
printk("pit %"PRId64"\n", pit->count_load_time[i]);
- pt = &pit->pt[i];
- if ( pt )
- {
- printk("pit channel %d has a periodic timer:\n", i);
- printk("pt %d.\n", pt->enabled);
- printk("pt %d.\n", pt->one_shot);
- printk("pt %d.\n", pt->irq);
- printk("pt %d.\n", pt->first_injected);
-
- printk("pt %d.\n", pt->pending_intr_nr);
- printk("pt %d.\n", pt->period);
- printk("pt %"PRId64"\n", pt->period_cycles);
- printk("pt %"PRId64"\n", pt->last_plt_gtime);
- }
}
+
+ pt = &pit->pt0;
+ printk("pit channel 0 periodic timer:\n", i);
+ printk("pt %d.\n", pt->enabled);
+ printk("pt %d.\n", pt->one_shot);
+ printk("pt %d.\n", pt->irq);
+ printk("pt %d.\n", pt->first_injected);
+ printk("pt %d.\n", pt->pending_intr_nr);
+ printk("pt %d.\n", pt->period);
+ printk("pt %"PRId64"\n", pt->period_cycles);
+ printk("pt %"PRId64"\n", pt->last_plt_gtime);
}
#else
static void pit_info(PITState *pit)
/* Recreate platform timers from hardware state. There will be some
* time jitter here, but the wall-clock will have jumped massively, so
* we hope the guest can handle it. */
+ pit->pt0.last_plt_gtime = hvm_get_guest_time(d->vcpu[0]);
for ( i = 0; i < 3; i++ )
- {
pit_load_count(pit, i, pit->hw.channels[i].count);
- pit->pt[i].last_plt_gtime = hvm_get_guest_time(d->vcpu[0]);
- }
pit_info(pit);
void pit_deinit(struct domain *d)
{
PITState *pit = domain_vpit(d);
- destroy_periodic_time(&pit->pt[0]);
+ destroy_periodic_time(&pit->pt0);
}
/* the intercept action for PIT DM retval:0--not handled; 1--handled */
static inline int pit_channel0_enabled(void)
{
PITState *pit = ¤t->domain->arch.hvm_domain.pl_time.vpit;
- struct periodic_time *pt = &pit->pt[0];
- return pt->enabled;
+ return pit->pt0.enabled;
}
static void vioapic_deliver(struct hvm_hw_vioapic *vioapic, int irq)
HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, ioapic_load, 1, HVMSR_PER_DOM);
-void vioapic_init(struct domain *d)
+int vioapic_init(struct domain *d)
{
- struct hvm_hw_vioapic *vioapic = domain_vioapic(d);
+ struct hvm_vioapic *vioapic;
int i;
- memset(vioapic, 0, sizeof(*vioapic));
+ vioapic = d->arch.hvm_domain.vioapic = xmalloc(struct hvm_vioapic);
+ if ( vioapic == NULL )
+ return -ENOMEM;
+
+ vioapic->domain = d;
+
+ memset(&vioapic->hvm_hw_vioapic, 0, sizeof(vioapic->hvm_hw_vioapic));
for ( i = 0; i < VIOAPIC_NUM_PINS; i++ )
- vioapic->redirtbl[i].fields.mask = 1;
- vioapic->base_address = VIOAPIC_DEFAULT_BASE_ADDRESS;
+ vioapic->hvm_hw_vioapic.redirtbl[i].fields.mask = 1;
+ vioapic->hvm_hw_vioapic.base_address = VIOAPIC_DEFAULT_BASE_ADDRESS;
+
+ return 0;
+}
+
+void vioapic_deinit(struct domain *d)
+{
+ xfree(d->arch.hvm_domain.vioapic);
+ d->arch.hvm_domain.vioapic = NULL;
}
#define VIOAPIC_REG_VERSION 0x01
#define VIOAPIC_REG_ARB_ID 0x02 /* x86 IOAPIC only */
-#define domain_vioapic(d) (&(d)->arch.hvm_domain.vioapic)
-#define vioapic_domain(v) (container_of((v), struct domain, \
- arch.hvm_domain.vioapic))
+struct hvm_vioapic {
+ struct hvm_hw_vioapic hvm_hw_vioapic;
+ struct domain *domain;
+};
-void vioapic_init(struct domain *d);
+#define domain_vioapic(d) (&(d)->arch.hvm_domain.vioapic->hvm_hw_vioapic)
+#define vioapic_domain(v) (container_of((v), struct hvm_vioapic, \
+ hvm_hw_vioapic)->domain)
+
+int vioapic_init(struct domain *d);
+void vioapic_deinit(struct domain *d);
void vioapic_irq_positive_edge(struct domain *d, unsigned int irq);
void vioapic_update_EOI(struct domain *d, int vector);