x86: enable CMT for each domain RMID

If the CMT service is attached to a domain, its related RMID
will be set to hardware for monitoring when the domain's vcpu is
scheduled in. When the domain's vcpu is scheduled out, RMID 0
(system reserved) will be set for monitoring.

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Release-Acked-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index d5133ac7c41d77283e501fcb9c5e6602ef5c5347..558d8d5e0bbb96640c1a4aea75a510571b31fbf5 100644 (file)
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1432,6 +1432,8 @@ static void __context_switch(void)
     {
         memcpy(&p->arch.user_regs, stack_regs, CTXT_SWITCH_STACK_BYTES);
         vcpu_save_fpu(p);
+        if ( psr_cmt_enabled() )
+            psr_assoc_rmid(0);
         p->arch.ctxt_switch_from(p);
     }
 
@@ -1456,6 +1458,9 @@ static void __context_switch(void)
         }
         vcpu_restore_fpu_eager(n);
         n->arch.ctxt_switch_to(n);
+
+        if ( psr_cmt_enabled() && n->domain->arch.psr_rmid > 0 )
+            psr_assoc_rmid(n->domain->arch.psr_rmid);
     }
 
     gdt = !is_pv_32on64_vcpu(n) ? per_cpu(gdt_table, cpu) :

diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index b6e9f2e0623722742b736599822b5100c5549bed..2ef83df982145ebe87649e4b9718fe305422fc4b 100644 (file)
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -20,10 +20,16 @@
 
 #define PSR_CMT        (1<<0)
 
+struct psr_assoc {
+    uint64_t val;
+    bool_t initialized;
+};
+
 struct psr_cmt *__read_mostly psr_cmt;
 static bool_t __initdata opt_psr;
 static unsigned int __initdata opt_rmid_max = 255;
 static uint64_t rmid_mask;
+static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
 
 static void __init parse_psr_param(char *s)
 {
@@ -162,6 +168,27 @@ void psr_free_rmid(struct domain *d)
     d->arch.psr_rmid = 0;
 }
 
+void psr_assoc_rmid(unsigned int rmid)
+{
+    uint64_t val;
+    uint64_t new_val;
+    struct psr_assoc *psra = &this_cpu(psr_assoc);
+
+    if ( !psra->initialized )
+    {
+        rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
+        psra->initialized = 1;
+    }
+    val = psra->val;
+
+    new_val = (val & ~rmid_mask) | (rmid & rmid_mask);
+    if ( val != new_val )
+    {
+        wrmsrl(MSR_IA32_PSR_ASSOC, new_val);
+        psra->val = new_val;
+    }
+}
+
 /*
  * Local variables:
  * mode: C

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 542222e07ac2a5e7244e0a429eda8464a1f3aa95..7214b40fe9af8e24390d66323f64ca24f0e7e460 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -323,6 +323,9 @@
 #define MSR_IA32_TSC_DEADLINE          0x000006E0
 #define MSR_IA32_ENERGY_PERF_BIAS      0x000001b0
 
+/* Platform Shared Resource MSRs */
+#define MSR_IA32_PSR_ASSOC             0x00000c8f
+
 /* Intel Model 6 */
 #define MSR_P6_PERFCTR(n)              (0x000000c1 + (n))
 #define MSR_P6_EVNTSEL(n)              (0x00000186 + (n))

diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 33f81f673c1cc390c1b74e2501cc78d342636db4..c6076e93005c7aae1d9d19460bdd0cfc949663f5 100644 (file)
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -46,6 +46,7 @@ static inline bool_t psr_cmt_enabled(void)
 
 int psr_alloc_rmid(struct domain *d);
 void psr_free_rmid(struct domain *d);
+void psr_assoc_rmid(unsigned int rmid);
 
 #endif /* __ASM_PSR_H__ */