if ( (rc = p2m_alloc_table(d)) != 0 )
goto fail;
- }
- if ( (rc = domain_vgic_init(d)) != 0 )
- goto fail;
+ if ( (rc = gicv_setup(d)) != 0 )
+ goto fail;
+
+ if ( (rc = domain_vgic_init(d)) != 0 )
+ goto fail;
+ }
/* Domain 0 gets a real UART not an emulated one */
if ( d->domain_id && (rc = domain_uart0_init(d)) != 0 )
rc = 0;
fail:
+ /*XXX unwind allocations etc */
return rc;
}
d->max_pages = ~0U;
- if ( (rc = p2m_alloc_table(d)) != 0 )
- return rc;
-
rc = prepare_dtb(d, &kinfo);
if ( rc < 0 )
return rc;
printk("Map VGIC MMIO regions 1:1 in the P2M %#llx->%#llx\n", 0x2C008000ULL, 0x2DFFFFFFULL);
map_mmio_regions(d, 0x2C008000, 0x2DFFFFFF, 0x2C008000);
- gicv_setup(d);
-
printk("Routing peripheral interrupts to guest\n");
/* TODO Get from device tree */
gic_route_irq_to_guest(d, 34, "timer0");
do_IRQ(regs, irq, is_fiq);
}
-void gicv_setup(struct domain *d)
+int gicv_setup(struct domain *d)
{
/* map the gic virtual cpu interface in the gic cpu interface region of
* the guest */
- printk("mapping GICC at %#"PRIx32" to %#"PRIx32"\n",
- GIC_BASE_ADDRESS + GIC_CR_OFFSET,
- GIC_BASE_ADDRESS + GIC_VR_OFFSET);
- map_mmio_regions(d, GIC_BASE_ADDRESS + GIC_CR_OFFSET,
+ return map_mmio_regions(d, GIC_BASE_ADDRESS + GIC_CR_OFFSET,
GIC_BASE_ADDRESS + GIC_CR_OFFSET + (2 * PAGE_SIZE) - 1,
GIC_BASE_ADDRESS + GIC_VR_OFFSET);
}
/* Take down a CPU's per-CPU GIC interface */
extern void gic_disable_cpu(void);
/* setup the gic virtual interface for a guest */
-extern void gicv_setup(struct domain *d);
+extern int gicv_setup(struct domain *d);
/* Context switch */
extern void gic_save_state(struct vcpu *v);
#include <xen/errno.h>
#include <xen/domain_page.h>
#include <asm/flushtlb.h>
+#include "gic.h"
void dump_p2m_lookup(struct domain *d, paddr_t addr)
{
BUG_ON(entry->p2m.valid);
- page = alloc_domheap_page(d, 0);
+ page = alloc_domheap_page(NULL, 0);
if ( page == NULL )
return -ENOMEM;