x86, idle: add barriers to CLFLUSH workaround

... since the documentation is explicit that CLFLUSH is only ordered
with respect to MFENCE.

Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index b05fb391824bf9927de604871b0c887d7ed8936c..136c0b63737509f81115563f41070293668e06da 100644 (file)
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -336,7 +336,11 @@ void mwait_idle_with_hints(unsigned int eax, unsigned int ecx)
     s_time_t expires = per_cpu(timer_deadline, cpu);
 
     if ( boot_cpu_has(X86_FEATURE_CLFLUSH_MONITOR) )
+    {
+        mb();
         clflush((void *)&mwait_wakeup(cpu));
+        mb();
+    }
 
     __monitor((void *)&mwait_wakeup(cpu), 0, 0);
     smp_mb();