update replace-dmb-instruction-with-coprocessor.patch

diff --git a/debian/patches/replace-dmb-instruction-with-coprocessor.patch b/debian/patches/replace-dmb-instruction-with-coprocessor.patch
index d23b3a9af52e40a59cb6d5e86c35b67c4885f3d8..f40b9aa0cdf131b7bde60e8791a44bee712bd658 100644 (file)
--- a/debian/patches/replace-dmb-instruction-with-coprocessor.patch
+++ b/debian/patches/replace-dmb-instruction-with-coprocessor.patch
@@ -7,10 +7,10 @@ Subject: replace dmb instruction with coprocessor barrier instruction.
 ---
 
 diff --git a/rts/include/stg/SMP.h b/rts/include/stg/SMP.h
-index 41cfc2c4..76ed1805 100644
+index bb30935a..bcf05e1f 100644
 --- a/rts/include/stg/SMP.h
 +++ b/rts/include/stg/SMP.h
-@@ -409,7 +409,7 @@ write_barrier(void) {
+@@ -487,7 +487,7 @@ write_barrier(void) {
  #elif defined(s390x_HOST_ARCH)
      __asm__ __volatile__ ("" : : : "memory");
  #elif defined(arm_HOST_ARCH) || defined(aarch64_HOST_ARCH)
@@ -18,8 +18,8 @@ index 41cfc2c4..76ed1805 100644
 +    __asm__ __volatile__ ("mcr p15, #0, r0, c7, c10, #5" : : : "memory");
  #elif defined(riscv64_HOST_ARCH)
      __asm__ __volatile__ ("fence w,w" : : : "memory");
- #else
-@@ -431,7 +431,7 @@ store_load_barrier(void) {
+ #elif defined(loongarch64_HOST_ARCH)
+@@ -511,7 +511,7 @@ store_load_barrier(void) {
  #elif defined(s390x_HOST_ARCH)
      __asm__ __volatile__ ("bcr 14,0" : : : "memory");
  #elif defined(arm_HOST_ARCH)
@@ -28,7 +28,7 @@ index 41cfc2c4..76ed1805 100644
  #elif defined(aarch64_HOST_ARCH)
      __asm__ __volatile__ ("dmb sy" : : : "memory");
  #elif defined(riscv64_HOST_ARCH)
-@@ -455,7 +455,7 @@ load_load_barrier(void) {
+@@ -537,7 +537,7 @@ load_load_barrier(void) {
  #elif defined(s390x_HOST_ARCH)
      __asm__ __volatile__ ("" : : : "memory");
  #elif defined(arm_HOST_ARCH)