[IA64] Put guest physical translation into VHPT
authorawilliam@xenbuild.aw <awilliam@xenbuild.aw>
Thu, 8 Jun 2006 17:08:35 +0000 (11:08 -0600)
committerawilliam@xenbuild.aw <awilliam@xenbuild.aw>
Thu, 8 Jun 2006 17:08:35 +0000 (11:08 -0600)
Signed-off-by: Anthony Xu <anthony.xu@intel.com>
xen/arch/ia64/vmx/vmx_phy_mode.c
xen/arch/ia64/vmx/vmx_process.c
xen/include/asm-ia64/vmx_phy_mode.h

index 95f827e2be10472c54f4df6d453bfc0df2abda3f..0ce402018acd59863ae1be61e80d5b0540a091d9 100644 (file)
@@ -105,55 +105,20 @@ physical_mode_init(VCPU *vcpu)
 }
 
 extern void vmx_switch_rr7(unsigned long ,shared_info_t*,void *,void *,void *);
-/*void
-physical_itlb_miss(VCPU *vcpu, u64 vadr)
-{
-    u64 psr;
-    IA64_PSR vpsr;
-    u64 xen_mppn,xen_gppn;
-    vpsr.val=vmx_vcpu_get_psr(vcpu);
-    xen_gppn=(vadr<<1)>>(PAGE_SHIFT+1);
-    xen_mppn = gmfn_to_mfn(vcpu->domain, xen_gppn);
-    xen_mppn=(xen_mppn<<PAGE_SHIFT)|(vpsr.cpl<<7);
-    if(vadr>>63)
-        xen_mppn |= PHY_PAGE_UC;
-    else
-        xen_mppn |= PHY_PAGE_WB;
 
-    psr=ia64_clear_ic();
-    ia64_itc(1,vadr&PAGE_MASK,xen_mppn,PAGE_SHIFT);
-    ia64_set_psr(psr);
-    ia64_srlz_i();
-    return;
-}
-
-*/
-/* 
- *      vec=1, itlb miss
- *      vec=2, dtlb miss
- */
 void
-physical_tlb_miss(VCPU *vcpu, u64 vadr, u64 vec)
+physical_tlb_miss(VCPU *vcpu, u64 vadr)
 {
-    u64 psr;
+    u64 pte;
     IA64_PSR vpsr;
-    u64 xen_mppn,xen_gppn;
     vpsr.val=vmx_vcpu_get_psr(vcpu);
-    xen_gppn=(vadr<<1)>>(PAGE_SHIFT+1);
-    xen_mppn = gmfn_to_mfn(vcpu->domain, xen_gppn);
-    xen_mppn=(xen_mppn<<PAGE_SHIFT)|(vpsr.cpl<<7);
-    if(vadr>>63)
-        xen_mppn |= PHY_PAGE_UC;
-    else
-        xen_mppn |= PHY_PAGE_WB;
-
-    psr=ia64_clear_ic();
-    ia64_itc(vec,vadr&PAGE_MASK,xen_mppn,PAGE_SHIFT);
-    ia64_set_psr(psr);
-    ia64_srlz_i();
+    pte =  vadr& _PAGE_PPN_MASK;
+    pte = pte|(vpsr.cpl<<7)|PHY_PAGE_WB;
+    thash_purge_and_insert(vcpu, pte, (PAGE_SHIFT<<2), vadr);
     return;
 }
 
+
 void
 vmx_init_all_rr(VCPU *vcpu)
 {
index c6e4d0220cd320494eeaa1dc00077642a0aa12ec..304a78a3f5d7d559e07825b05abcda33c7f9178e 100644 (file)
@@ -259,7 +259,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
                 return IA64_FAULT;
             }
         }
-        physical_tlb_miss(v, vadr, vec);
+        physical_tlb_miss(v, vadr);
         return IA64_FAULT;
     }
     if(vec == 1) type = ISIDE_TLB;
index 8cc35352c07360d13419bbc5627909b9d6e908bb..02f8cc643fa34a035fe5fc1ece577914f3bb52f2 100644 (file)
@@ -96,7 +96,7 @@ extern void prepare_if_physical_mode(VCPU *vcpu);
 extern void recover_if_physical_mode(VCPU *vcpu);
 extern void vmx_init_all_rr(VCPU *vcpu);
 extern void vmx_load_all_rr(VCPU *vcpu);
-extern void physical_tlb_miss(VCPU *vcpu, u64 vadr, u64 vec);
+extern void physical_tlb_miss(VCPU *vcpu, u64 vadr);
 /*
  * No sanity check here, since all psr changes have been
  * checked in switch_mm_mode().